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| ? 2007 microchip technology inc. preliminary ds39774c pic18f85j11 family data sheet 64/80-pin high-performance microcontrollers with nanowatt technology
ds39774c-page ii preliminary ? 2007 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered tr ademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, linear active thermistor, migratable memory, mxdev, mxlab, ps logo, seeval, smartsensor and the embedded control solutions company are registered trademarks of micr ochip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powe rtool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona, gresham, oregon and mountain view, california. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ? 2007 microchip technology inc. preliminary ds39774c-page 1 pic18f85j11 family peripheral highlights: ? high-current sink/source 25 ma/25 ma (portb and portc) ? up to four external interrupts ? four 8-bit/16-bit timer/counter modules ? real-time clock (rtc) software module: - configurable 24-hour clock, calendar, automatic 100-year or 12800-year day of week calculator using timer1 ? two capture/compare/pwm (ccp) modules: - capture is 16-bit, max. resolution 6.25 ns (t cy /16) - compare is 16-bit, max. resolution 100 ns (t cy ) - pwm output: pwm resolution is up to 10-bit ? master synchronous serial port (mssp) module with two modes of operation: - 3-wire/4-wire spi (supports all 4 spi modes) -i 2 c? master and slave mode ? one addressable usart module ? one enhanced addressable usart module: - supports lin 1.2 - auto-wake-up on start bit and break character - auto-baud detect (abd) ? 10-bit, up to 12-channel a/d converter: - auto-acquisition - conversion available during sleep ? two analog comparators ? programmable reference voltage for comparators external memory bus (pic18f8xj11 only): ? address capability of up to 2 mbytes ? 8-bit or 16-bit interface ? 12-bit, 16-bit and 20-bit addressing modes low-power features: ? power-managed modes: run, idle, sleep ? run current down to 9 a, typical ? idle current down to 2.5 a, typical ? sleep current down to 100 na, typical ? fast intosc start-up from sleep ? two-speed oscillator start-up reduces crystal stabilization wait time flexible oscillator structure: ? two crystal modes, 4-25 mhz ? two external clock modes, up to 40 mhz ? 4x phase lock loop (pll) ? internal oscillator block: - 8 user-selectable frequencies from 31.25 khz to 8 mhz ? secondary oscillator using timer1 @ 32 khz ? fail-safe clock monitor: - allows for safe shutdown if peripheral clock fails special microcontroller features: ? 1,000 erase/write cycle flash program memory typical ? flash retention 20 years minimum ? self-programmable under software control ? priority levels for interrupts ? 8 x 8 single-cycle hardware multiplier ? extended watchdog timer (wdt): - programmable period from 4 ms to 131s ? in-circuit serial programming? (icsp?) via two pins ? in-circuit debug via two pins ? operating voltage range: 2.0v to 3.6v ? 5.5v tolerant input (digital pins only) ? selectable open-drain configuration for serial communication and ccp pins for driving outputs up to 5v ? on-chip 2.5v regulator device program memory sram data memory (bytes) i/o timers 8/16-bit ccp mssp eusart/ ausart 10-bit a/d (ch) comparators bor/lvd external bus psp flash (bytes) # single-word instructions spi master i 2 c? pic18f63j11 8k 4096 1k 52 1/3 2 y y 1/1 12 2 y n y pic18f64j11 16k 8192 1k 52 1/3 2 y y 1/1 12 2 y n y pic18f65j11 32k 16384 2k 52 1/3 2 y y 1/1 12 2 y n y pic18f83j11 8k 4096 1k 68 1/3 2 y y 1/1 12 2 y y y pic18f84j11 16k 8192 1k 68 1/3 2 y y 1/1 12 2 y y y pic18f85j11 32k 16384 2k 68 1/3 2 y y 1/1 12 2 y y y 64/80-pin high-performance microcontrollers with nanowatt technology pic18f85j11 family ds39774c-page 2 preliminary ? 2007 microchip technology inc. pin diagrams 64-pin tqfp pic18f63j11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 38 37 36 35 34 33 50 49 17 18 19 20 21 22 23 24 25 26 15 16 31 40 39 27 28 29 30 32 48 47 46 45 44 43 42 41 54 53 52 51 58 57 56 55 60 59 64 63 62 61 note 1: the ccp2 pin placement depends on the ccp2mx configuration bit setting. re2/cs re3 re4 re5 re6 re7/ccp2 (1) rd0/psp0 v dd v ss rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 rb0/int0 rb1/int1 rb2/int2 rb3/int3 rb4/kbi0 rb5/kbi1 rb6/kbi2/pgc v ss ra6/osc2/clko ra7/osc1/clki v dd rb7/kbi3/pgd rc2/ccp1 rc5/sdo rc4/sdi/sda rc3/sck/scl envreg rf1/an6/c2out av dd av ss ra3/an2/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/an4 rc1/t1osi/ccp2 (1) rc0/t1oso/t13cki rc7/rx1/dt1 rc6/tx1/ck1 re1/wr re0/rd rg0 rg1/tx2/ck2 rg2/rx2/dt2 rg3 mclr rg4 v ss v ddcore /v cap rf7/an5/ss rf6/an11 rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out pic18f64j11 pic18f65j11 ? 2007 microchip technology inc. preliminary ds39774c-page 3 pic18f85j11 family pin diagrams (continued) 80-pin tqfp 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 1 2 17 18 37 50 49 19 20 33 34 35 36 38 58 57 56 55 54 53 52 51 60 59 68 67 66 65 72 71 70 69 74 73 78 77 76 75 79 80 note 1: the ccp2 pin placement depends on the settings of the ccp2mx and emb1:emb0 configuration bits. rb0/int0 rb1/int1 rb2/int2 rb3/int3/ccp2 (1) rb4/kbi0 rb5/kbi1 rb6/kbi2/pgc v ss ra6/osc2/clko ra7/osc1/clki v dd rb7/kbi3/pgd rc2/ccp1 rc5/sdo rj7/ub rj6/lb rj2/wrl rj3/wrh rc4/sdi/sda rc3/sck/scl re1/wr /ad9 re0/rd /ad8 rg0 rg1/tx2/ck2 rg2/rx2/dt2 rg3 mclr rg4 v ss v ddcore /v cap rf7/an5/ss rh2/a18 rh3/a19 rh7 rh6 rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rf6/an11 re2/ad10/cs re3/ad11 re4/ad12 re5/ad13 re6/ad14 re7/ad15/ccp2 (1) rd0/ad0/psp0 v dd v ss rd1/ad1/psp1 rd2/ad2/psp2 rd3/ad3/psp3 rd4/ad4/psp4 rd5/ad5/psp5 rd6/ad6/psp6 rd7/ad7/psp7 rj0/ale rj1/oe rh1/a17 rh0/a16 envreg rf1/an6/c2out av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/an4 rc1/t1osi/ccp2 (1) rc0/t1oso/t13cki rc7/rx1/dt1 rc6/tx1/ck1 rh5 rh4 rj5/ce rj4/ba0 pic18f83j11 pic18f84j11 pic18f85j11 pic18f85j11 family ds39774c-page 4 preliminary ? 2007 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 7 2.0 oscillator configurations ................................................................................................... ......................................................... 29 3.0 power-managed modes ......................................................................................................... .................................................... 37 4.0 reset ....................................................................................................................... ................................................................... 45 5.0 memory organization ......................................................................................................... ........................................................ 57 6.0 flash program memory........................................................................................................ ...................................................... 83 7.0 external memory bus ......................................................................................................... ........................................................ 93 8.0 8 x 8 hardware multiplier................................................................................................... ....................................................... 105 9.0 interrupts .................................................................................................................. ................................................................ 107 10.0 i/o ports .................................................................................................................. ................................................................. 123 11.0 timer0 module .............................................................................................................. ........................................................... 147 12.0 timer1 module .............................................................................................................. ........................................................... 151 13.0 timer2 module .............................................................................................................. ........................................................... 157 14.0 timer3 module .............................................................................................................. ........................................................... 159 15.0 capture/compare/pwm (ccp) modules .......................................................................................... ....................................... 163 16.0 master synchronous serial port (mssp) module ............................................................................... ..................................... 173 17.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) .................................................. ............. 217 18.0 addressable universal synchronous asynchr onous receiver transmitter (ausart) ............................................... ............ 237 19.0 10-bit analog-to-digital converter (a/d) module ............................................................................ .......................................... 251 20.0 comparator module.......................................................................................................... ........................................................ 261 21.0 comparator voltage reference module ........................................................................................ ........................................... 267 22.0 special features of the cpu ................................................................................................ .................................................... 271 23.0 instruction set summary .................................................................................................... ...................................................... 285 24.0 development support........................................................................................................ ....................................................... 335 25.0 electrical characteristics ................................................................................................. ......................................................... 339 26.0 dc and ac characteristics graphs and tables ................................................................................ ....................................... 373 27.0 packaging information...................................................................................................... ........................................................ 375 appendix a: revision history................................................................................................... .......................................................... 379 appendix b: migration between high-end device families......................................................................... ...................................... 379 index .......................................................................................................................... ........................................................................ 381 the microchip web site ......................................................................................................... ............................................................ 391 customer change notification service ........................................................................................... ................................................... 391 customer support ............................................................................................................... ............................................................... 391 reader response ................................................................................................................ .............................................................. 392 product identification system.................................................................................................. ........................................................... 393 ? 2007 microchip technology inc. preliminary ds39774c-page 5 pic18f85j11 family to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/doc umentation issues become known to us, we will publis h an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. pic18f85j11 family ds39774c-page 6 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. preliminary ds39774c-page 7 pic18f85j11 family 1.0 device overview this document contains device-specific information for the following devices: this family combines the traditional advantages of all pic18 microcontrollers ? namely, high computational performance and a rich feature set ? while maintaining an extremely competitive price point. these features make the pic18f85j11 family a logical choice for many high-performance applications where price is a primary consideration. 1.1 core features 1.1.1 nanowatt technology all of the devices in the pic18f85j11 family incorporate a range of features that c an significantly reduce power consumption during operation. key items include: ? alternate run modes: by clocking the controller from the timer1 source or the internal rc oscillator, power consumption during code execution can be reduced by as much as 90%. ? multiple idle modes: the controller can also run with its cpu core disabled but the peripherals still active. in these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. ? on-the-fly mode switching: the power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application?s software design. 1.1.2 oscillator options and features all of the devices in the pic18f85j11 family offer six different oscillator options, allowing users a range of choices in developing application hardware. these include: ? two crystal modes, using crystals or ceramic resonators. ? two external clock modes, offering the option of a divide-by-4 clock output. ? a phase lock loop (pll) frequency multiplier, available to the external oscillator modes, which allows clock speeds of up to 40 mhz. ? an internal oscillator block which provides an 8 mhz clock (2% accuracy) and an intrc source (approximately 31 khz, stable over temperature and v dd ), as well as a range of six user-selectable clock frequencies, between 125 khz to 4 mhz, for a total of eight clock frequencies. this option frees the two oscillator pins for use as additional general purpose i/o. the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: ? fail-safe clock monitor: this option constantly monitors the main clock source against a reference signal provided by the internal oscillator. if a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. ? two-speed start-up: this option allows the internal oscillator to serve as the clock source from power-on reset, or wake-up from sleep mode, until the primary clock source is available. 1.1.3 memory options the pic18f85j11 family provides a range of program memory options, from 8 kbytes to 32 kbytes of code space. the flash cells for program memory are rated to last up to 1000 erase/write cycles. data retention without refresh is conservatively estimated to be greater than 20 years. the pic18f85j11 family also provides plenty of room for dynamic application data, with up to 2048 bytes of data ram. 1.1.4 extended instruction set the pic18f85j11 family implements the optional extension to the pic18 instruction set, adding 8 new instructions and an indexed addressing mode. enabled as a device configuration option, the extension has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as ?c?. 1.1.5 external memory bus in the event that 32 kbytes of memory are inadequate for an application, the 80-pin members of the pic18f85j11 family also implement an external mem- ory bus. this allows the controller?s internal program counter to address a memory space of up to 2 mbytes, permitting a level of data access that few 8-bit devices can claim. this allows additional memory options, including: ? using combinations of on-chip and external memory up to the 2-mbyte limit ? using external flash memory for reprogrammable application code or large data tables ? using external ram devices for storing large amounts of variable data ? pic18f63j11 ? pic18f83j11 ? pic18f64j11 ? pic18f84j11 ? pic18f65j11 ? pic18f85j11 pic18f85j11 family ds39774c-page 8 preliminary ? 2007 microchip technology inc. 1.1.6 easy migration regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. the consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. this is true when moving between the 64-pin members, between the 80-pin members or even jumping from 64-pin to 80-pin devices. the pic18f85j11 family is also largely pin compatible with other pic18 general purpose families, such as the pic18f8720 and pic18f8722. this allows a new dimension to the evolution of applications, allowing developers to select different price points within microchip?s pic18 portfolio, while maintaining a similar feature set. 1.2 other special features ? communications: the pic18f85j11 family incorporates a range of serial communication peripherals, including an addressable usart, a separate enhanced usart that supports lin specification 1.2, and one master ssp (mssp) module capable of both spi and i 2 c? (master and slave) modes of operation. ? ccp modules: all devices in the family incorporate two capture/compare/pwm (ccp) modules. up to four different time bases may be used to perform several different operations at once. ? 10-bit a/d converter: this module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reducing code overhead. ? extended watchdog timer (wdt): this enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. see section 25.0 ?electrical characteristics? for time-out periods. 1.3 details on individual family members devices in the pic18f85j11 family are available in 64-pin and 80-pin packages. block diagrams for the two groups are shown in figure 1-1 and figure 1-2. the devices are differentiated from each other in four ways: 1. flash program memory (three sizes, ranging from 8 kbytes for pic18fx3j11 devices to 32 kbytes for pic18fx5j11 devices). 2. data ram (1024 bytes for pic18fx3j11 and pic18fx4j11 devices, 2048 bytes for pic18fx5j11 devices). 3. i/o ports (7 bidirectional ports on 64-pin devices, 9 bidirectional ports on 80-pin devices). 4. external memory bus (implemented in 80-pin devices only). all other features for devices in this family are identical. these are summarized in table 1-1 and table 1-2. the pinouts for all devices are listed in table 1-3 and table 1-4. ? 2007 microchip technology inc. preliminary ds39774c-page 9 pic18f85j11 family table 1-1: device features for the pic18f6xj11 family (64-pin devices) table 1-2: device features for the pic18f8xj11 family (80-pin devices) features pic18f63j11 pic18f64j11 pic18f65j11 operating frequency dc ? 40 mhz program memory (bytes) 8k 16k 32k program memory (instructions) 4096 8192 16384 data memory (bytes) 1024 1024 2048 interrupt sources 27 i/o ports ports a, b, c, d, e, f, g timers 4 capture/compare/pwm modules 2 serial communications mssp, addressable usart, enhanced usart parallel communications (psp) yes external memory bus no 10-bit analog-to-digital module 12 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow, mclr , wdt (pwrt, ost) instruction set 75 instructions, 83 with extended instruction set enabled packages 64-pin tqfp features pic18f83j11 pic18f84j11 pic18f85j11 operating frequency dc ? 40 mhz program memory (bytes) 8k 16k 32k program memory (instructions) 4096 8192 16384 data memory (bytes) 1024 1024 2048 interrupt sources 27 i/o ports ports a, b, c, d, e, f, g, h, j timers 4 capture/compare/pwm modules 2 serial communications mssp, addressable usart, enhanced usart parallel communications (psp) yes external memory bus yes 10-bit analog-to-digital module 12 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow, mclr , wdt (pwrt, ost) instruction set 75 instructions, 83 with extended instruction set enabled packages 80-pin tqfp pic18f85j11 family ds39774c-page 10 preliminary ? 2007 microchip technology inc. figure 1-1: pic18f6xj11 (6 4-pin) block diagram instruction decode and control porta data latch data memory (3.9 kbytes) address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> address latch program memory (96 kbytes) data latch 20 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 pclatu pcu w instruction bus <16> stkptr bank 8 state machine control signals decode 8 8 rom latch portc portd porte portf portg ra0:ra7 (1,2) rc0:rc7 (1) rd0:rd7 (1) re0:re7 (1) rf1:rf7 (1) rg0:rg4 (1) portb rb0:rb7 (1) ausart comparators mssp timer2 timer1 timer3 timer0 ccp1 adc 10-bit eusart ccp2 osc1/clki osc2/clko v dd , v ss mclr power-up timer oscillator start-up timer power-on reset watchdog timer precision reference band gap regulator voltage v ddcore /v cap envreg timing generation intrc oscillator 8 mhz oscillator bor and lvd (3) note 1: see table 1-3 for i/o port pin descriptions. 2: ra6 and ra7 are only available as digital i/o in select oscillator modes. see section 2.0 ?oscillator configurations? for more information 3: brown-out reset and low-voltage detect functions are provided when the on-board voltage regulator is enabled. ? 2007 microchip technology inc. preliminary ds39774c-page 11 pic18f85j11 family figure 1-2: pic18f8xj11 (80-pin) block diagram prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> 8 8 3 w 8 8 8 instruction decode & control data latch data memory (3.9 kbytes) address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4 12 4 pch pcl pclath 8 31 level stack program counter address latch program memory (128 kbytes) data latch 20 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 rom latch pclatu pcu instruction bus <16> stkptr bank state machine control signals decode system bus interface ad15:ad0, a19:a16 (multiplexed with portd, porte and porth) porta portc portd porte portf portg ra0:ra7 (1,2) rc0:rc7 (1) rd0:rd7 (1) re0:re7 (1) rf1:rf7 (1) rg0:rg4 (1) portb rb0:rb7 (1) porth rh0:rh7 (1) portj rj0:rj7 (1) ausart comparators mssp timer2 timer1 timer3 timer0 ccp1 adc 10-bit eusart ccp2 osc1/clki osc2/clko v dd , v ss mclr power-up timer oscillator start-up timer power-on reset watchdog timer precision reference band gap regulator voltage v ddcore /v cap envreg timing generation intrc oscillator 8 mhz oscillator bor and lvd (3) note 1: see table 1-3 for i/o port pin descriptions. 2: ra6 and ra7 are only available as digital i/o in select oscillator modes. see section 2.0 ?oscillator configurations? for more information 3: brown-out reset and low-voltage detect functions are provided when the on-board voltage regulator is enabled. pic18f85j11 family ds39774c-page 12 preliminary ? 2007 microchip technology inc. table 1-3: pic18f6xj11 pinout i/o descriptions pin name pin number pin type buffer type description tqfp mclr 7 i st master clear (input) or programming voltage (input). this pin is an active-low reset to the device. ra7/osc1/clki ra7 osc1 clki 39 i/o i i ttl cmos cmos oscillator crystal or external clock input. general purpose i/o pin. oscillator crystal input. external clock source input. always associated with pin function osc1. (see related osc1/clki, osc2/clko pins.) ra6/osc2/clko ra6 osc2 clko 40 i/o o o ttl ? ? oscillator crystal or clock output. general purpose i/o pin. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in ec modes, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. porta is a bidirectional i/o port. ra0/an0 ra0 an0 24 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 23 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 22 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 21 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 28 i/o i st/od st digital i/o. open-drain when configured as output. timer0 external clock input. ra5/an4 ra5 an4 27 i/o i ttl analog digital i/o. analog input 4. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. ? 2007 microchip technology inc. preliminary ds39774c-page 13 pic18f85j11 family portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0 rb0 int0 48 i/o i ttl st digital i/o. external interrupt 0. rb1/int1 rb1 int1 47 i/o i ttl st digital i/o. external interrupt 1. rb2/int2 rb2 int2 46 i/o i ttl st digital i/o. external interrupt 2. rb3/int3 rb3 int3 45 i/o i ttl st digital i/o. external interrupt 3. rb4/kbi0 rb4 kbi0 44 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb5/kbi1 rb5 kbi1 43 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb6/kbi2/pgc rb6 kbi2 pgc 42 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp? programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 37 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-3: pic18f6xj11 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. pic18f85j11 family ds39774c-page 14 preliminary ? 2007 microchip technology inc. portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 30 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 (1) 29 i/o i i/o st cmos st digital i/o. timer1 oscillator input. capture 2 input/compare 2 output/pwm2 output. rc2/ccp1 rc2 ccp1 33 i/o i/o st st digital i/o. capture 1 input/compare 1 output/pwm1 output. rc3/sck/scl rc3 sck scl 34 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi/sda rc4 sdi sda 35 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 36 i/o o st ? digital i/o. spi data out. rc6/tx1/ck1 rc6 tx1 ck1 31 i/o o i/o st ? st digital i/o. eusart asynchronous transmit. eusart synchronous clock (see related rx1/dt1). rc7/rx1/dt1 rc7 rx1 dt1 32 i/o i i/o st st st digital i/o. eusart asynchronous receive. eusart synchronous data (see related tx1/ck1). table 1-3: pic18f6xj11 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. ? 2007 microchip technology inc. preliminary ds39774c-page 15 pic18f85j11 family portd is a bidirectional i/o port. rd0/psp0 rd0 psp0 58 i/o i/o st ttl digital i/o. parallel slave port data. rd1/psp1 rd1 psp1 55 i/o i/o st ttl digital i/o. parallel slave port data. rd2/psp2 rd2 psp2 54 i/o i/o st ttl digital i/o. parallel slave port data. rd3/psp3 rd3 psp3 53 i/o i/o st ttl digital i/o. parallel slave port data. rd4/psp4 rd4 psp4 52 i/o i/o st ttl digital i/o. parallel slave port data. rd5/psp5 rd5 psp5 51 i/o i/o st ttl digital i/o. parallel slave port data. rd6/psp6 rd6 psp6 50 i/o i/o st ttl digital i/o. parallel slave port data. rd7/psp7 rd7 psp7 49 i/o i/o st ttl digital i/o. parallel slave port data. table 1-3: pic18f6xj11 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. pic18f85j11 family ds39774c-page 16 preliminary ? 2007 microchip technology inc. porte is a bidirectional i/o port. re0/rd re0 rd 2 i/o i st ttl digital i/o. read control for parallel slave port. re1/wr re1 wr 1 i/o i st ttl digital i/o. write control for parallel slave port. re2/cs re2 cs 64 i/o i st ttl digital i/o. chip select control for parallel slave port. re3 63 i/o st digital i/o. re4 62 i/o st digital i/o. re5 61 i/o st digital i/o. re6 60 i/o st digital i/o. re7/ccp2 re7 ccp2 (2) 59 i/o i/o st st digital i/o. capture 2 input/compare 2 output/pwm2 output. table 1-3: pic18f6xj11 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. ? 2007 microchip technology inc. preliminary ds39774c-page 17 pic18f85j11 family portf is a bidirectional i/o port. rf1/an6/c2out rf1 an6 c2out 17 i/o i o st analog ? digital i/o. analog input 6. comparator 2 output. rf2/an7/c1out rf2 an7 c1out 16 i/o i o st analog ? digital i/o. analog input 7. comparator 1 output. rf3/an8 rf3 an8 15 i/o i st analog digital i/o. analog input 8. rf4/an9 rf4 an9 14 i/o i st analog digital i/o. analog input 9. rf5/an10/cv ref rf5 an10 cv ref 13 i/o i o st analog analog digital i/o. analog input 10. comparator reference voltage output. rf6/an11 rf6 an11 12 i/o i st analog digital i/o. analog input 11. rf7/an5/ss rf7 an5 ss 11 i/o o i st analog ttl digital i/o. analog input 5. spi slave select input. table 1-3: pic18f6xj11 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. pic18f85j11 family ds39774c-page 18 preliminary ? 2007 microchip technology inc. portg is a bidirectional i/o port. rg0 3 i/o st digital i/o. rg1/tx2/ck2 rg1 tx2 ck2 4 i/o o i/o st ? st digital i/o. ausart asynchronous transmit. ausart synchronous clock (see related rx2/dt2). rg2/rx2/dt2 rg2 rx2 dt2 5 i/o i i/o st st st digital i/o. ausart asynchronous receive. ausart synchronous data (see related tx2/ck2). rg3 6 i/o st digital i/o. rg4 8 i/o st digital i/o. v ss 9, 25, 41, 56 p ? ground reference for logic and i/o pins. v dd 26, 38, 57 p ? positive supply for logic and i/o pins. av ss 20 p ? ground reference for analog modules. av dd 19 p ? positive supply for analog modules. envreg 18 i st enable for on-chip voltage regulator. v ddcore /v cap v ddcore v cap 10 p p ? ? core logic power or external filter capacitor connection. positive supply for microcontroller core logic (regulator disabled). external filter capacitor connection (regulator enabled). table 1-3: pic18f6xj11 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. ? 2007 microchip technology inc. preliminary ds39774c-page 19 pic18f85j11 family table 1-4: pic18f8xj11 pinout i/o descriptions pin name pin number pin type buffer type description tqfp mclr 9 i st master clear (input) or programming voltage (input). this pin is an active-low reset to the device. ra7/osc1/clki ra7 osc1 clki 49 i/o i i ttl cmos cmos oscillator crystal or external clock input. general purpose i/o pin. oscillator crystal input. external clock source input. always associated with pin function osc1. (see related osc1/clki, osc2/clko pins.) ra6/osc2/clko ra6 osc2 clko 50 i/o o o ttl ? ? oscillator crystal or clock output. general purpose i/o pin. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in ec modes, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. porta is a bidirectional i/o port. ra0/an0 ra0 an0 30 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 29 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 28 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 27 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 34 i/o i st/od st digital i/o. open-drain when configured as output. timer0 external clock input. ra5/an4 ra5 an4 33 i/o i ttl analog digital i/o. analog input 4. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when ccp2mx configuration bit is cleared (80-pin devices, extended microcontroller mode only). 2: default assignment for ccp2 when ccp2mx configuration bit is set. 3: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. pic18f85j11 family ds39774c-page 20 preliminary ? 2007 microchip technology inc. portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0 rb0 int0 58 i/o i ttl st digital i/o. external interrupt 0. rb1/int1 rb1 int1 57 i/o i ttl st digital i/o. external interrupt 1. rb2/int2 rb2 int2 56 i/o i ttl st digital i/o. external interrupt 2. rb3/int3/ccp2 rb3 int3 ccp2 (1) 55 i/o i i/o ttl st st digital i/o. external interrupt 3. capture 2 input/compare 2 output/pwm2 output. rb4/kbi0 rb4 kbi0 54 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb5/kbi1 rb5 kbi1 53 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb6/kbi2/pgc rb6 kbi2 pgc 52 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp? programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 47 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-4: pic18f8xj11 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when ccp2mx configuration bit is cleared (80-pin devices, extended microcontroller mode only). 2: default assignment for ccp2 when ccp2mx configuration bit is set. 3: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. ? 2007 microchip technology inc. preliminary ds39774c-page 21 pic18f85j11 family portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 36 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 (2) 35 i/o i i/o st cmos st digital i/o. timer1 oscillator input. capture 2 input/compare 2 output/pwm2 output. rc2/ccp1 rc2 ccp1 43 i/o i/o st st digital i/o. capture 1 input/compare 1 output/pwm1 output. rc3/sck/scl rc3 sck scl 44 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi/sda rc4 sdi sda 45 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 46 i/o o st ? digital i/o. spi data out. rc6/tx1/ck1 rc6 tx1 ck1 37 i/o o i/o st ? st digital i/o. eusart asynchronous transmit. eusart synchronous clock (see related rx1/dt1). rc7/rx1/dt1 rc7 rx1 dt1 38 i/o i i/o st st st digital i/o. eusart asynchronous receive. eusart synchronous data (see related tx1/ck1). table 1-4: pic18f8xj11 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when ccp2mx configuration bit is cleared (80-pin devices, extended microcontroller mode only). 2: default assignment for ccp2 when ccp2mx configuration bit is set. 3: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. pic18f85j11 family ds39774c-page 22 preliminary ? 2007 microchip technology inc. portd is a bidirectional i/o port. rd0/ad0/psp0 rd0 ad0 psp0 72 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 0. parallel slave port data. rd1/ad1/psp1 rd1 ad1 psp1 69 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 1. parallel slave port data. rd2/ad2/psp2 rd2 ad2 psp2 68 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 2. parallel slave port data. rd3/ad3/psp3 rd3 ad3 psp3 67 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 3. parallel slave port data. rd4/ad4/psp4 rd4 ad4 psp4 66 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 4. parallel slave port data. rd5/ad5/psp5 rd5 ad5 psp5 65 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 5. parallel slave port data. rd6/ad6/psp6 rd6 ad6 psp6 64 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 6. parallel slave port data. rd7/ad7/psp7 rd7 ad7 psp7 63 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 7. parallel slave port data. table 1-4: pic18f8xj11 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when ccp2mx configuration bit is cleared (80-pin devices, extended microcontroller mode only). 2: default assignment for ccp2 when ccp2mx configuration bit is set. 3: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. ? 2007 microchip technology inc. preliminary ds39774c-page 23 pic18f85j11 family porte is a bidirectional i/o port. re0/rd /ad8 re0 rd ad8 4 i/o i i/o st ttl ttl digital i/o. read control for parallel slave port. external memory address/data 8. re1/wr /ad9 re1 wr ad9 3 i/o i i/o st ttl ttl digital i/o. write control for parallel slave port. external memory address/data 9. re2/ad10/cs re2 ad10 cs 78 i/o i/o i st ttl ttl digital i/o. external memory address/data 10. chip select control for parallel slave port. re3/ad11 re3 ad11 77 i/o i/o st ttl digital i/o. external memory address/data 11. re4/ad12 re4 ad12 76 i/o i/o st ttl digital i/o. external memory address/data 12. re5/ad13 re5 ad13 75 i/o i/o st ttl digital i/o. external memory address/data 13. re6/ad14 re6 ad14 74 i/o i/o st ttl digital i/o. external memory address/data 14. re7/ad15/ccp2 re7 ad15 ccp2 (3) 73 i/o i/o i/o st ttl st digital i/o. external memory address/data 15. capture 2 input/compare 2 output/pwm2 output. table 1-4: pic18f8xj11 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when ccp2mx configuration bit is cleared (80-pin devices, extended microcontroller mode only). 2: default assignment for ccp2 when ccp2mx configuration bit is set. 3: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. pic18f85j11 family ds39774c-page 24 preliminary ? 2007 microchip technology inc. portf is a bidirectional i/o port. rf1/an6/c2out rf1 an6 c2out 23 i/o i o st analog ? digital i/o. analog input 6. comparator 2 output. rf2/an7/c1out rf2 an7 c1out 18 i/o i o st analog ? digital i/o. analog input 7. comparator 1 output. rf3/an8 rf3 an8 17 i/o i st analog digital i/o. analog input 8. rf4/an9 rf4 an9 16 i/o i st analog digital i/o. analog input 9. rf5/an10/cv ref rf5 an10 cv ref 15 i/o i o st analog analog digital i/o. analog input 10. comparator reference voltage output. rf6/an11 rf6 an11 14 i/o i st analog digital i/o. analog input 11. rf7/an5/ss rf7 an5 ss 13 i/o o i st analog ttl digital i/o. analog input 5. spi slave select input. table 1-4: pic18f8xj11 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when ccp2mx configuration bit is cleared (80-pin devices, extended microcontroller mode only). 2: default assignment for ccp2 when ccp2mx configuration bit is set. 3: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. ? 2007 microchip technology inc. preliminary ds39774c-page 25 pic18f85j11 family portg is a bidirectional i/o port. rg0 5 i/o st digital i/o. rg1/tx2/ck2 rg1 tx2 ck2 6 i/o o i/o st ? st digital i/o. ausart asynchronous transmit. ausart synchronous clock (see related rx2/dt2). rg2/rx2/dt2 rg2 rx2 dt2 7 i/o i i/o st st st digital i/o. ausart asynchronous receive. ausart synchronous data (see related tx2/ck2). rg3 8 i/o st digital i/o. rg4 10 i/o st digital i/o. table 1-4: pic18f8xj11 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when ccp2mx configuration bit is cleared (80-pin devices, extended microcontroller mode only). 2: default assignment for ccp2 when ccp2mx configuration bit is set. 3: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. pic18f85j11 family ds39774c-page 26 preliminary ? 2007 microchip technology inc. porth is a bidirectional i/o port. rh0/a16 rh0 a16 79 i/o i/o st ttl digital i/o. external memory address/data 16. rh1/a17 rh1 a17 80 i/o i/o st ttl digital i/o. external memory address/data 17. rh2/a18 rh2 a18 1 i/o i/o st ttl digital i/o. external memory address/data 18. rh3/a19 rh3 a19 2 i/o i/o st ttl digital i/o. external memory address/data 19. rh4 22 i/o st digital i/o. rh5 21 i/o st digital i/o. rh6 20 i/o st digital i/o. rh7 19 i/o st digital i/o. table 1-4: pic18f8xj11 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when ccp2mx configuration bit is cleared (80-pin devices, extended microcontroller mode only). 2: default assignment for ccp2 when ccp2mx configuration bit is set. 3: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. ? 2007 microchip technology inc. preliminary ds39774c-page 27 pic18f85j11 family portj is a bidirectional i/o port. rj0/ale rj0 ale 62 i/o o st ? digital i/o. external memory address latch enable. rj1/oe rj1 oe 61 i/o o st ? digital i/o. external memory output enable. rj2/wrl rj2 wrl 60 i/o o st ? digital i/o. external memory write low control. rj3/wrh rj3 wrh 59 i/o o st ? digital i/o. external memory write high control. rj4/ba0 rj4 ba0 39 i/o o st ? digital i/o. external memory byte address 0 control. rj5/ce rj5 ce 40 i/o o st ? digital i/o external memory chip enable control. rj6/lb rj6 lb 41 i/o o st ? digital i/o. external memory low byte control. rj7/ub rj7 ub 42 i/o o st ? digital i/o. external memory high byte control. v ss 11, 31, 51, 70 p ? ground reference for logic and i/o pins. v dd 32, 48, 71 p ? positive supply for logic and i/o pins. av ss 26 p ? ground reference for analog modules. av dd 25 p ? positive supply for analog modules. envreg 24 i st enable for on-chip voltage regulator. v ddcore /v cap v ddcore v cap 12 p p ? ? core logic power or external filter capacitor connection. positive supply for microcontroller core logic (regulator disabled). external filter capacitor connection (regulator enabled). table 1-4: pic18f8xj11 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when ccp2mx configuration bit is cleared (80-pin devices, extended microcontroller mode only). 2: default assignment for ccp2 when ccp2mx configuration bit is set. 3: alternate assignment for ccp2 when ccp2mx configuration bit is cleared. pic18f85j11 family ds39774c-page 28 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. preliminary ds39774c-page 29 pic18f85j11 family 2.0 oscillator configurations 2.1 oscillator types the pic18f85j11 family of devices can be operated in six different oscillator modes: 1. hs high-speed crystal/resonator 2. hspll high-speed crystal/resonator with software pll control 3. ec external clock with f osc /4 output 4. ecpll external clock with software pll control 5. intosc internal fast rc (8 mhz) oscillator 6. intrc internal 31 khz oscillator five of these are selected by the user by programming the fosc2:fosc0 configuration bits. the sixth mode (intrc) may be invoked under software control; it can also be configured as the default mode on device resets. in addition, pic18f85j11 family devices can switch between different clock sources, either under software control or automatically under certain conditions. this allows for additional power savings by managing device clock speed in real time without resetting the application. the clock sources for the pic18f85j11 family of devices are shown in figure 2-1. figure 2-1: pic18f85j11 family clock diagram pic18f85j11 family 4 x pll fosc2:fosc0 secondary oscillator t1oscen enable oscillator t1oso t1osi clock source option for other modules osc1 osc2 sleep hspll, ecpll hs, ec t1osc cpu peripherals idlen postscaler mux mux 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 125 khz 250 khz osccon<6:4> 111 110 101 100 011 010 001 000 31 khz intrc source internal oscillator block wdt, pwrt, fscm 8 mhz internal oscillator (intosc) osccon<6:4> clock control osccon<1:0> source 8 mhz 31 khz (intrc) 0 1 osctune<7> and two-speed start-up primary oscillator pic18f85j11 family ds39774c-page 30 preliminary ? 2007 microchip technology inc. 2.2 control registers the osccon register (register 2-1) controls the main aspects of the device clock?s operation. it selects the oscillator type to be used, which of the power-managed modes to invoke and the output frequency of the intosc source. it also provides status on the oscillators. the osctune register (register 2-2) controls the tuning and operation of the internal oscillator block. it also implements the pllen bits which control the operation of the phase locked loop (pll) in internal oscillator modes (see section 2.4.3 ?pll frequency multiplier? ). register 2-1: osccon: oscillator control register r/w-0 r/w-1 r/w-0 r/w-0 r (1) r-0 r/w-0 r/w-0 idlen ircf2 (2) ircf1 (2) ircf0 (2) osts iofs scs1 (4) scs0 (4) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 idlen: idle enable bit 1 = device enters an idle mode when a sleep instruction is executed 0 = device enters sleep mode when a sleep instruction is executed bit 6-4 ircf2:ircf0: intosc source frequency select bits (2) 111 = 8 mhz (intosc drives clock directly) 110 = 4mhz 101 = 2mhz 100 = 1 mhz (default) 011 = 500khz 010 = 250khz 001 = 125khz 000 = 31 khz (from either intosc/256 or intrc) (3) bit 3 osts: oscillator start-up time-out status bit (1) 1 = oscillator start-up timer (ost) time-out has expired; primary oscillator is running 0 = oscillator start-up timer (ost) time-out is running; primary oscillator is not ready bit 2 iofs: intosc frequency stable bit 1 = fast rc oscillator frequency is stable 0 = fast rc oscillator frequency is not stable bit 1-0 scs1:scs0: system clock select bits (4) 11 = internal oscillator block 10 = primary oscillator 01 = timer1 oscillator when fosc2 = 1 : 00 = primary oscillator when fosc2 = 0 : 00 = internal oscillator note 1: reset state depends on state of the ieso configuration bit. 2: modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. 3: source selected by the intsrc bit (osctune<7>), see text. 4: modifying these bits will cause an immediate clock source switch. ? 2007 microchip technology inc. preliminary ds39774c-page 31 pic18f85j11 family 2.3 clock sources and oscillator switching essentially, pic18f85j11 family devices have three independent clock sources: ? primary oscillators ? secondary oscillators ? internal oscillator the primary oscillators can be thought of as the main device oscillators. these are any external oscillators connected to the osc1 and osc2 pins, and include the external crystal and resonator modes and the external clock modes. in some circumstances, the internal oscillator block may be considered a primary oscillator. the particular mode is defined by the fosc configuration bits. the details of these modes are covered in section 2.4 ?external oscillator modes? . the secondary oscillators are external clock sources that are not connected to the osc1 or osc2 pins. these sources may continue to operate even after the controller is placed in a power-managed mode. pic18f85j11 family devices offer the timer1 oscillator as a secondary oscillator source. this oscillator, in all power-managed modes, is often the time base for functions such as a real-time clock. the timer1 oscil- lator is discussed in greater detail in section 12.3 ?timer1 oscillator? in addition to being a primary clock source in some cir- cumstances, the internal oscillator is available as a power-managed mode clock source. the intrc source is also used as the clock source for several special features, such as the wdt and fail-safe clock monitor. the internal oscillator block is discussed in more detail in section 2.5 ?internal oscillator block? . the pic18f85j11 family includes features that allow the device clock source to be switched from the main oscillator, chosen by device configuration, to one of the alternate clock sources. when an alternate clock source is enabled, various power-managed operating modes are available. register 2-2: osctune: oscillator tuning register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 intsrc pllen (1) tun5 tun4 tun3 tun2 tun1 tun0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 intsrc: internal oscillator low-frequency source select bit 1 = 31.25 khz device clock derived from 8 mhz intosc source (divide-by-256 enabled) 0 = 31 khz device clock derived from intrc 31 khz oscillator bit 6 pllen: frequency multiplier pll enable bit (1) 1 = pll enabled 0 = pll disabled bit 5-0 tun5:tun0: fast rc oscillator (intosc) frequency tuning bits 011111 = maximum frequency ? ? ? ? 000001 000000 = center frequency. fast rc oscillator is running at the calibrated frequency. 111111 ? ? ? ? 100000 = minimum frequency note 1: available only for ecpll and hspll oscillator configurations; otherwise, this bit is unavailable and reads as ? 0 ?. pic18f85j11 family ds39774c-page 32 preliminary ? 2007 microchip technology inc. 2.3.1 clock source selection the system clock select bits, scs1:scs0 (osccon<1:0>), select the clock source. the avail- able clock sources are the primary clock, defined by the fosc1:fosc0 configuration bits, the secondary clock (timer1 oscillator) and the internal oscillator. the clock source changes after one or more of the bits are written to, following a brief clock transition interval. the osts (osccon<3>) and t1run (t1con<6>) bits indicate which clock source is currently providing the device clock. the osts bit indicates that the oscillator start-up timer (ost) has timed out and the primary clock is providing the device clock in primary clock modes. the t1run bit indicates when the timer1 oscillator is providing the device clock in sec- ondary clock modes. in power-managed modes, only one of these bits will be set at any time. if neither of these bits are set, the intrc is providing the clock, or the internal oscillator has just started and is not yet stable. the idlen bit determines if the device goes into sleep mode or one of the idle modes when the sleep instruction is executed. the use of the flag and control bits in the osccon register is discussed in more detail in section 3.0 ?power-managed modes? . 2.3.1.1 system clock selection and the fosc2 configuration bit the scs bits are cleared on all forms of reset. in the device?s default configuration, this means the primary oscillator defined by fosc1:fosc0 (that is, one of the hs or ec modes) is used as the primary clock source on device resets. the default clock configuration on reset can be changed with the fosc2 configuration bit. this bit determines whether the external or internal oscillator will be the default clock source on subsequent device resets. by extension, it also has the effect of determin- ing the clock source selected when scs1:scs0 are in their reset state (= 00 ). when fosc2 = 1 (default), the oscillator source defined by fosc1:fosc0 is selected whenever scs1:scs0 = 00 . when fosc2 = 0 , the internal oscillator block is selected whenever scs1:scs2 = 00 . in those cases when the internal oscillator block is the default clock on reset, the fast rc oscillator (intosc) will be used as the device clock source. it will initially start at 1 mhz; the postscaler selection that corresponds to the reset value of the ircf2:ircf0 bits (? 100 ?). regardless of the setting of fosc2, intrc will always be enabled on device power-up. it serves as the clock source until the device has loaded its configuration values from memory. it is at this point that the fosc configuration bits are read and the oscillator selection of the operational mode is made. note that either the primary clock or the internal oscillator will have two bit setting options for the possible values of scs1:scs0, at any given time, depending on the setting of fosc2. 2.3.2 oscillator transitions pic18f85j11 family devices contain circuitry to prevent clock ?glitches? when switching between clock sources. a short pause in the device clock occurs dur- ing the clock switch. the length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. this formula assumes that the new clock source is stable. clock transitions are discussed in greater detail in section 3.1.2 ?entering power-managed modes? . note 1: the timer1 oscillator must be enabled to select the secondary clock source. the timer1 oscillator is enabled by setting the t1oscen bit in the timer1 control regis- ter (t1con<3>). if the timer1 oscillator is not enabled, then any attempt to select a secondary clock source when executing a sleep instruction will be ignored. 2: it is recommended that the timer1 oscillator be operating and stable before executing the sleep instruction or a very long delay may occur while the timer1 oscillator starts. ? 2007 microchip technology inc. preliminary ds39774c-page 33 pic18f85j11 family 2.4 external oscillator modes 2.4.1 crystal oscillator/ceramic resonators (hs modes) in hs or hspll oscillator modes, a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation. figure 2-2 shows the pin connections. the oscillator design requires the use of a parallel cut crystal. table 2-1: capacitor selection for ceramic resonators table 2-2: capacitor selection for crystal oscillator figure 2-2: crystal/ceramic resonator operation (hs or hspll configuration) note: use of a series cut crystal may give a fre- quency out of the crystal manufacturer?s specifications. typical capacitor values used: mode freq. osc1 osc2 hs 8.0 mhz 16.0 mhz 27 pf 22 pf 27 pf 22 pf capacitor values are for design guidance only. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. refer to the following application notes for oscillator specific information: ? an588, ?pic ? microcontroller oscillator design guide? ? an826, ?crystal oscillator basics and crystal selection for rfpic ? and pic ? devices? ? an849, ?basic pic ? oscillator design? ? an943, ?practical pic ? oscillator analysis and design? ? an949, ?making your oscillator work? see the notes following table 2-2 for additional information. osc type crystal freq. typical capacitor values tested: c1 c2 hs 4 mhz 27 pf 27 pf 8 mhz 22 pf 22 pf 20 mhz 15 pf 15 pf capacitor values are for design guidance only. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. refer to the microchip application notes cited in table 2-1 for oscillator specific information. also see the notes following this table for additional information. note 1: higher capacitance increases the stability of oscillator but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: rs may be required to avoid overdriving crystals with low drive level specification. 4: always verify oscillator performance over the v dd and temperature range that is expected for the application. note 1: see table 2-1 and table 2-2 for initial values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: r f varies with the oscillator mode chosen. c1 (1) c2 (1) xtal osc2 osc1 r f (3) sleep to logic pic18f85j11 r s (2) internal pic18f85j11 family ds39774c-page 34 preliminary ? 2007 microchip technology inc. 2.4.2 external clock input (ec modes) the ec and ecpll oscillator modes require an exter- nal clock source to be connected to the osc1 pin. there is no oscillator start-up time required after a power-on reset or after an exit from sleep mode. in the ec oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-3 shows the pin connections for the ec oscillator mode. figure 2-3: external clock input operation (ec configuration) an external clock source may also be connected to the osc1 pin in the hs mode, as shown in figure 2-4. in this configuration, the divide-by-4 output on osc2 is not available. figure 2-4: external clock input operation (hs osc configuration) 2.4.3 pll frequency multiplier a phase locked loop (pll) circuit is provided as an option for users who want to use a lower frequency oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. this may be useful for customers who are concerned with emi due to high-frequency crystals, or users who require higher clock speeds from an internal oscillator. for these reasons, the hspll and ecpll modes are available. the hspll and ecpll modes provide the ability to selectively run the device at 4 times the external oscil- lating source to produce frequencies up to 40 mhz. the pll is enabled by programming the fosc2:fosc0 configuration bits (config2l<2:0>) to either ? 110 ? (for ecpll) or ? 100 ? (for hspll). in addition, the pllen bit (osctune<6>) must also be set. clearing pllen disables the pll, regardless of the chosen oscillator configuration. it also allows additional flexibility for controlling the application?s clock speed in software. figure 2-5: pll block diagram osc1/clki osc2/clko f osc /4 clock from ext. system pic18f85j11 or ra6 osc1 osc2 open clock from ext. system pic18f85j11 (hs mode) mux vco loop filter osc2 osc1 pll enable (osctune) f in f out sysclk phase comparator hspll or ecpll (config2l) 4 hs or ec mode ? 2007 microchip technology inc. preliminary ds39774c-page 35 pic18f85j11 family 2.5 internal oscillator block the pic18f85j11 family of devices includes an internal oscillator block which generates two different clock signals; either can be used as the microcontroller?s clock source. this may eliminate the need for an external oscillator circuit on the osc1 and/or osc2 pins. the main output is the fast rc oscillator, or intosc, an 8 mhz clock source which can be used to directly drive the device clock. it also drives a postscaler which can provide a range of clock frequencies from 31 khz to 4 mhz. intosc is enabled when a clock frequency from 125 khz to 8 mhz is selected. the intosc out- put can also be enabled when 31 khz is selected, depending on the intsrc bit (osctune<7>). the other clock source is the internal rc oscillator (intrc), which provides a nominal 31 khz output. intrc is enabled if it is selected as the device clock source. it is also enabled automatically when any of the following are enabled: ? power-up timer ? fail-safe clock monitor ? watchdog timer ? two-speed start-up these features are discussed in greater detail in section 22.0 ?special features of the cpu? . the clock source frequency (intosc direct, intosc with postscaler or intrc direct) is selected by config- uring the ircf bits of the osccon register. the default frequency on device resets is 1 mhz. 2.5.1 osc1 and osc2 pin configuration whenever the internal oscillator is configured as the default clock source (fosc2 = 0 ), the osc1 and osc2 pins are reconfigured automatically as port pins, ra6 and ra7. in this mode, they function as general digital i/o. all oscillator functions on the pins are disabled. 2.5.2 internal oscillator output frequency and tuning the internal oscillator block is calibrated at the factory to produce an intosc output frequency of 8 mhz. it can be adjusted in the user?s application by writing to tun5:tun0 (osctune<5:0>) in the osctune register (register 2-2). when the osctune register is modified, the intosc frequency will begin shifting to the new frequency. the oscillator will stabilize within 1 ms. code execution con- tinues during this shift. there is no indication that the shift has occurred. the intrc oscillator operates independently of the intosc source. any changes in intosc across voltage and temperature are not necessarily reflected by changes in intrc or vice versa. the frequency of intrc is not affected by osctune. 2.5.3 intosc frequency drift the intosc frequency may drift as v dd or tempera- ture changes, and can affect the controller operation in a variety of ways. it is possible to adjust the intosc frequency by modifying the value in the osctune register. this will have no effect on the intrc clock source frequency. tuning intosc requires knowing when to make the adjustment, in which direction it should be made, and in some cases, how large a change is needed. three compensation techniques are shown here. 2.5.3.1 compensating with the eusart an adjustment may be required when the eusart begins to generate framing errors or receives data with errors while in asynchronous mode. framing errors indicate that the device clock frequency is too high. to adjust for this, decrement the value in osctune to reduce the clock frequency. on the other hand, errors in data may suggest that the clock speed is too low. to compensate, increment osctune to increase the clock frequency. 2.5.3.2 compensating with the timers this technique compares device clock speed to some reference clock. two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the timer1 oscillator. both timers are cleared, but the timer clocked by the reference generates interrupts. when an interrupt occurs, the internally clocked timer is read and both timers are cleared. if the internally clocked timer value is much greater than expected, then the internal oscillator block is running too fast. to adjust for this, decrement the osctune register. 2.5.3.3 compensating with the ccp module in capture mode a ccp module can use free-running timer1 (or timer3), clocked by the internal oscillator block and an external event with a known period (i.e., ac power frequency). the time of the first event is captured in the ccprxh:ccprxl registers and is recorded for use later. when the second event causes a capture, the time of the first event is subtracted from the time of the second event. since the period of the external event is known, the time difference between events can be calculated. if the measured time is much greater than the calculated time, the internal oscillator block is running too fast. to compensate, decrement the osctune register. if the measured time is much less than the calculated time, the internal oscillator block is running too slow. to compensate, increment the osctune register. pic18f85j11 family ds39774c-page 36 preliminary ? 2007 microchip technology inc. 2.6 effects of power-managed modes on the various clock sources when pri_idle mode is selected, the designated pri- mary oscillator continues to run without interruption. for all other power-managed modes, the oscillator using the osc1 pin is disabled. the osc1 pin (and osc2 pin if used by the oscillator) will stop oscillating. in secondary clock modes (sec_run and sec_idle), the timer1 oscillator is operating and providing the device clock. the timer1 oscillator may also run in all power-managed modes if required to clock timer1 or timer3. in rc_run and rc_idle modes, the internal oscilla- tor provides the device clock source. the 31 khz intrc output can be used directly to provide the clock and may be enabled to support various special features, regardless of the power-managed mode (see section 22.2 ?watchdog timer (wdt)? through section 22.5 ?fail-safe clock monitor? for more information on wdt, fail-safe clock monitor and two-speed start-up). if the sleep mode is selected, all clock sources are stopped. since all the transistor switching currents have been stopped, sleep mode achieves the lowest current consumption of the device (only leakage currents). enabling any on-chip feature that will operate during sleep will increase the current consumed during sleep. the intrc is required to support wdt operation. the timer1 oscillator may be operating to support a real- time clock (rtc). other features may be operating that do not require a device clock source (i.e., mssp slave, psp, intn pins and others). peripherals that may add significant current consumption are listed in section 25.2 ?dc characteristics: power-down and supply current? . 2.7 power-up delays power-up delays are controlled by two timers, so that no external reset circuitry is required for most applica- tions. the delays ensure that the device is kept in reset until the device power supply is stable under nor- mal circumstances and the primary clock is operating and stable. for additional information on power-up delays, see section 4.6 ?power-up timer (pwrt)? . the first timer is the power-up timer (pwrt), which provides a fixed delay on power-up (parameter 33, table 25-10). it is always enabled. the second timer is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable (hs modes). the ost does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. there is a delay of interval t csd (parameter 38, table 25-10), following por, while the controller becomes ready to execute instructions. table 2-3: osc1 and osc2 pin states in sleep mode oscillator mode osc1 pin osc2 pin ec, ecpll floating, pulled by external clock at logic low (clock/4 output) hs, hspll feedback inverter disabled at quiescent voltage level feedback inverter disabled at quiescent voltage level intosc i/o pin, ra6, direction controlled by trisa<6> i/o pin, ra7, direction controlled by trisa<7> note: see table 4-2 in section 4.0 ?reset? for time-outs due to sleep and mclr reset. ? 2007 microchip technology inc. preliminary ds39774c-page 37 pic18f85j11 family 3.0 power-managed modes the pic18f85j11 family devices provide the ability to manage power consumption by simply managing clock- ing to the cpu and the peripherals. in general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. for the sake of managing power in an application, there are three primary modes of operation: ? run mode ? idle mode ? sleep mode these modes define which portions of the device are clocked and at what speed. the run and idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block); the sleep mode does not use a clock source. the power-managed modes include several power-saving features offered on previous pic ? mcus. one is the clock switching feature, offered in other pic18 devices, allowing the controller to use the timer1 oscillator in place of the primary oscillator. also included is the sleep mode, offered by all pic mcus, where all device clocks are stopped. 3.1 selecting power-managed modes selecting a power-managed mode requires two decisions: if the cpu is to be clocked or not and which clock source is to be used. the idlen bit (osccon<7>) controls cpu clocking, while the scs1:scs0 bits (osccon<1:0>) select the clock source. the individual modes, bit settings, clock sources and affected modules are summarized in table 3-1. 3.1.1 clock sources the scs1:scs0 bits allow the selection of one of three clock sources for power-managed modes. they are: ? the primary clock, as defined by the fosc2:fosc0 configuration bits ? the secondary clock (timer1 oscillator) ? the internal oscillator 3.1.2 entering power-managed modes switching from one power-managed mode to another begins by loading the osccon register. the scs1:scs0 bits select the clock source and determine which run or idle mode is to be used. changing these bits causes an immediate switch to the new clock source, assuming that it is running. the switch may also be subject to clock transition delays. these are discussed in section 3.1.3 ?clock transitions and status indicators? and subsequent sections. entry to the power-managed idle or sleep modes is triggered by the execution of a sleep instruction. the actual mode that results depends on the status of the idlen bit. depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. many transitions may be done by changing the oscillator select bits, or changing the idlen bit, prior to issuing a sleep instruction. if the idlen bit is already configured correctly, it may only be necessary to perform a sleep instruction to switch to the desired mode. table 3-1: power-managed modes mode osccon bits module clocking available clock and oscillator source idlen<7> (1) scs1:scs0<1:0> cpu peripherals sleep 0 n/a off off none ? all clocks are disabled pri_run n/a 10 clocked clocked primary ? hs, ec, hspll, ecpll; this is the normal, full power execution mode sec_run n/a 01 clocked clocked secondary ? timer1 oscillator rc_run n/a 11 clocked clocked internal oscillator pri_idle 110 off clocked primary ? hs, ec, hspll, ecpll sec_idle 101 off clocked secondary ? timer1 oscillator rc_idle 111 off clocked internal oscillator note 1: idlen reflects its value when the sleep instruction is executed. pic18f85j11 family ds39774c-page 38 preliminary ? 2007 microchip technology inc. 3.1.3 clock transitions and status indicators the length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. this formula assumes that the new clock source is stable. two bits indicate the current clock source and its status: osts (osccon<3>) and t1run (t1con<6>). in general, only one of these bits will be set while in a given power-managed mode. when the osts bit is set, the primary clock is providing the device clock. when the t1run bit is set, the timer1 oscillator is providing the clock. if neither of these bits is set, intrc is clocking the device. 3.1.4 multiple sleep commands the power-managed mode that is invoked with the sleep instruction is determined by the setting of the idlen bit at the time the instruction is executed. if another sleep instruction is executed, the device will enter the power-managed mode specified by idlen at that time. if idlen has changed, the device will enter the new power-managed mode specified by the new setting. 3.2 run modes in the run modes, clocks to both the core and peripherals are active. the difference between these modes is the clock source. 3.2.1 pri_run mode the pri_run mode is the normal, full power execution mode of the microcontroller. this is also the default mode upon a device reset unless two-speed start-up is enabled (see section 22.4 ?two-speed start-up? for details). in this mode, the osts bit is set (see section 2.2 ?control registers? ). 3.2.2 sec_run mode the sec_run mode is the compatible mode to the ?clock switching? feature offered in other pic18 devices. in this mode, the cpu and peripherals are clocked from the timer1 oscillator. this gives users the option of lower power consumption while still using a high-accuracy clock source. sec_run mode is entered by setting the scs1:scs0 bits to ? 01 ?. the device clock source is switched to the timer1 oscillator (see figure 3-1), the primary oscilla- tor is shut down, the t1run bit (t1con<6>) is set and the osts bit is cleared. note: executing a sleep instruction does not necessarily place the device into sleep mode. it acts as the trigger to place the controller into either the sleep mode, or one of the idle modes, depending on the setting of the idlen bit. ? 2007 microchip technology inc. preliminary ds39774c-page 39 pic18f85j11 family on transitions from sec_run mode to pri_run mode, the peripherals and cpu continue to be clocked from the timer1 oscillator while the primary clock is started. when the primary clock becomes ready, a clock switch back to the primary clock occurs (see figure 3-2). when the clock switch is complete, the t1run bit is cleared, the osts bit is set and the primary clock is providing the clock. the idlen and scs bits are not affected by the wake-up; the timer1 oscillator continues to run. figure 3-1: transition timing for entry to sec_run mode figure 3-2: transition timing from sec_run mode to pri_run mode (hspll) note: the timer1 oscillator should already be running prior to entering sec_run mode. if the t1oscen bit is not set when the scs1:scs0 bits are set to ? 01 ?, entry to sec_run mode will not occur. if the timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. in such situa- tions, initial oscillator operation is far from stable and unpredictable operation may result. q4 q3 q2 osc1 peripheral program q1 t1osi q1 counter clock cpu clock pc + 2 pc 123 n-1 n clock transition q4 q3 q2 q1 q3 q2 pc + 4 q1 q3 q4 osc1 peripheral program pc t1osi pll clock q1 pc + 4 q2 output q3 q4 q1 cpu clock pc + 2 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. scs1:scs0 bits changed t pll (1) 12 n-1n clock osts bit set transition t ost (1) pic18f85j11 family ds39774c-page 40 preliminary ? 2007 microchip technology inc. 3.2.3 rc_run mode in rc_run mode, the cpu and peripherals are clocked from the internal oscillator; the primary clock is shut down. this mode provides the best power conser- vation of all the run modes while still executing code. it works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times. this mode is entered by setting scs bits to ? 11 ?. when the clock source is switched to the intrc (see figure 3-3), the primary oscillator is shut down and the osts bit is cleared. on transitions from rc_run mode to pri_run mode, the device continues to be clocked from the intrc while the primary clock is started. when the primary clock becomes ready, a clock switch to the primary clock occurs (see figure 3-4). when the clock switch is complete, the osts bit is set and the primary clock is providing the device clock. the idlen and scs bits are not affected by the switch. the intrc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. figure 3-3: transition timing to rc_run mode figure 3-4: transition timing fr om rc_run mode to pri_run mode q4 q3 q2 osc1 peripheral program q1 intrc q1 counter clock cpu clock pc + 2 pc 123 n-1n clock transition q4 q3 q2 q1 q3 q2 pc + 4 q1 q3 q4 osc1 peripheral program pc intrc pll clock q1 pc + 4 q2 output q3 q4 q1 cpu clock pc + 2 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. scs1:scs0 bits changed t pll (1) 12 n-1n clock osts bit set transition t ost (1) ? 2007 microchip technology inc. preliminary ds39774c-page 41 pic18f85j11 family 3.3 sleep mode the power-managed sleep mode is identical to the legacy sleep mode offered in all other pic micro- controllers. it is entered by clearing the idlen bit (the default state on device reset) and executing the sleep instruction. this shuts down the selected oscillator (figure 3-5). all clock source status bits are cleared. entering the sleep mode from any other mode does not require a clock switch. this is because no clocks are needed once the controller has entered sleep. if the wdt is selected, the intrc source will continue to operate. if the timer1 oscillator is enabled, it will also continue to run. when a wake event occurs in sleep mode (by interrupt, reset or wdt time-out), the device will not be clocked until the clock source selected by the scs1:scs0 bits becomes ready (see figure 3-6), or it will be clocked from the internal oscillator if either the two-speed start-up or the fail-safe clock monitor is enabled (see section 22.0 ?special features of the cpu? ). in either case, the osts bit is set when the primary clock is providing the device clocks. the idlen and scs bits are not affected by the wake-up. 3.4 idle modes the idle modes allow the controller?s cpu to be selectively shut down while the peripherals continue to operate. selecting a particular idle mode allows users to further manage power consumption. if the idlen bit is set to a ? 1 ? when a sleep instruction is executed, the peripherals will be clocked from the clock source selected using the scs1:scs0 bits; however, the cpu will not be clocked. the clock source status bits are not affected. setting idlen and executing a sleep instruction provides a quick method of switching from a given run mode to its corresponding idle mode. if the wdt is selected, the intrc source will continue to operate. if the timer1 oscillator is enabled, it will also continue to run. since the cpu is not executing instructions, the only exits from any of the idle modes are by interrupt, wdt time-out or a reset. when a wake event occurs, cpu execution is delayed by an interval of t csd (parameter 38, table 25-10) while it becomes ready to execute code. when the cpu begins executing code, it resumes with the same clock source for the current idle mode. for example, when waking from rc_idle mode, the internal oscillator block will clock the cpu and peripherals (in other words, rc_run mode). the idlen and scs bits are not affected by the wake-up. while in any idle mode or the sleep mode, a wdt time-out will result in a wdt wake-up to the run mode currently specified by the scs1:scs0 bits. figure 3-5: transition timing for entry to sleep mode figure 3-6: transition timing for wake from sleep (hspll) q4 q3 q2 osc1 peripheral sleep program q1 q1 counter clock cpu clock pc + 2 pc q3 q4 q1 q2 osc1 peripheral program pc pll clock q3 q4 output cpu clock q1 q2 q3 q4 q1 q2 clock counter pc + 6 pc + 4 q1 q2 q3 q4 wake event note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. t ost (1) t pll (1) osts bit set pc + 2 pic18f85j11 family ds39774c-page 42 preliminary ? 2007 microchip technology inc. 3.4.1 pri_idle mode this mode is unique among the three low-power idle modes, in that it does not disable the primary device clock. for timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to ?warm up? or transition from another oscillator. pri_idle mode is entered from pri_run mode by setting the idlen bit and executing a sleep instruc- tion. if the device is in another run mode, set idlen first, then set the scs bits to ? 10 ? and execute sleep . although the cpu is disabled, the peripherals continue to be clocked from the primary clock source specified by the fosc1:fosc0 configuration bits. the osts bit remains set (see figure 3-7). when a wake event occurs, the cpu is clocked from the primary clock source. a delay of interval t csd is required between the wake event and when code exe- cution starts. this is required to allow the cpu to become ready to execute instructions. after the wake-up, the osts bit remains set. the idlen and scs bits are not affected by the wake-up (see figure 3-8). 3.4.2 sec_idle mode in sec_idle mode, the cpu is disabled but the peripherals continue to be clocked from the timer1 oscillator. this mode is entered from sec_run by set- ting the idlen bit and executing a sleep instruction. if the device is in another run mode, set idlen first, then set scs1:scs0 to ? 01 ? and execute sleep . when the clock source is switched to the timer1 oscillator, the primary oscillator is shut down, the osts bit is cleared and the t1run bit is set. when a wake event occurs, the peripherals continue to be clocked from the timer1 oscillator. after an interval of t csd following the wake event, the cpu begins exe- cuting code being clocked by the timer1 oscillator. the idlen and scs bits are not affected by the wake-up; the timer1 oscillator continues to run (see figure 3-8). figure 3-7: transition timing for entry to idle mode figure 3-8: transition timing for wake from idle to run mode note: the timer1 oscillator should already be running prior to entering sec_idle mode. if the t1oscen bit is not set when the sleep instruction is executed, the sleep instruction will be ignored and entry to sec_idle mode will not occur. if the timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. in such situations, initial oscillator operation is far from stable and unpredictable operation may result. q1 peripheral program pc pc + 2 osc1 q3 q4 q1 cpu clock clock counter q2 osc1 peripheral program pc cpu clock q1 q3 q4 clock counter q2 wake event t csd ? 2007 microchip technology inc. preliminary ds39774c-page 43 pic18f85j11 family 3.4.3 rc_idle mode in rc_idle mode, the cpu is disabled but the periph- erals continue to be clocked from the internal oscillator. this mode allows for controllable power conservation during idle periods. from rc_run, this mode is entered by setting the idlen bit and executing a sleep instruction. if the device is in another run mode, first set idlen, then clear the scs bits and execute sleep . when the clock source is switched to the intrc, the primary oscillator is shut down and the osts bit is cleared. when a wake event occurs, the peripherals continue to be clocked from the intosc. after a delay of t csd following the wake event, the cpu begins executing code being clocked by the intosc. the idlen and scs bits are not affected by the wake-up. the intosc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. 3.5 exiting idle and sleep modes an exit from sleep mode, or any of the idle modes, is triggered by an interrupt, a reset or a wdt time-out. this section discusses the triggers that cause exits from power-managed modes. the clocking subsystem actions are discussed in each of the power-managed mode sections (see section 3.2 ?run modes?, section 3.3 ?sleep mode? and section 3.4 ?idle modes? ). 3.5.1 exit by interrupt any of the available interrupt sources can cause the device to exit from an idle mode, or the sleep mode, to a run mode. to enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the intcon or pie registers. the exit sequence is initiated when the corresponding interrupt flag bit is set. on all exits from idle or sleep modes by interrupt, code execution branches to the interrupt vector if the gie/gieh bit (intcon<7>) is set. otherwise, code execution continues or resumes without branching (see section 9.0 ?interrupts? ). a fixed delay of interval t csd following the wake event is required when leaving sleep and idle modes. this delay is required for the cpu to prepare for execution. instruction execution resumes on the first clock cycle following this delay. 3.5.2 exit by wdt time-out a wdt time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. if the device is not executing code (all idle modes and sleep mode), the time-out will result in an exit from the power-managed mode (see section 3.2 ?run modes? and section 3.3 ?sleep mode? ). if the device is executing code (all run modes), the time-out will result in a wdt reset (see section 22.2 ?watchdog timer (wdt)? ). the watchdog timer and postscaler are cleared by one of the following events: ? executing a sleep or clrwdt instruction ? the loss of a currently selected clock source (if the fail-safe clock monitor is enabled) 3.5.3 exit by reset exiting an idle or sleep mode by reset automatically forces the device to run from the intrc. 3.5.4 exit without an oscillator start-up delay certain exits from power-managed modes do not invoke the ost at all. there are two cases: ? pri_idle mode, where the primary clock source is not stopped; and ? the primary clock source is either the ec or ecpll mode. in these instances, the primary clock source either does not require an oscillator start-up delay, since it is already running (pri_idle), or normally does not require an oscillator start-up delay (ec). however, a fixed delay of interval t csd following the wake event is still required when leaving sleep and idle modes to allow the cpu to prepare for execution. instruction execution resumes on the first clock cycle following this delay. pic18f85j11 family ds39774c-page 44 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. preliminary ds39774c-page 45 pic18f85j11 family 4.0 reset the pic18f85j11 family of devices differentiate between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during power-managed modes d) watchdog timer (wdt) reset (during execution) e) brown-out reset (bor) f) reset instruction g) stack full reset h) stack underflow reset this section discusses resets generated by mclr , por and bor, and covers the operation of the various start-up timers. stack reset events are covered in section 5.1.6.4 ?stack full and underflow resets? . wdt resets are covered in section 22.2 ?watchdog timer (wdt)? . a simplified block diagram of the on-chip reset circuit is shown in figure 4-1. 4.1 rcon register device reset events are tracked through the rcon register (register 4-1). the lower five bits of the register indicate that a specific reset event has occurred. in most cases, these bits can only be set by the event and must be cleared by the application after the event. the state of these flag bits, taken together, can be read to indicate the type of reset that just occurred. this is described in more detail in section 4.7 ?reset state of registers? . the rcon register also has a control bit for setting interrupt priority (ipen). interrupt priority is discussed in section 9.0 ?interrupts? . figure 4-1: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd wdt time-out v dd rise detect pwrt intrc por pulse pwrt chip_reset 11-bit ripple counter brown-out reset (1) reset instruction stack pointer stack full/underflow reset sleep ( )_idle 65.5 ms 32 s note 1: the envreg pin must be tied high to enable brown-out re set. the brown-out reset is provided by the on-chip voltage regulator when there is insufficient source voltage to maintain regulation. pic18f85j11 family ds39774c-page 46 preliminary ? 2007 microchip technology inc. register 4-1: rcon: reset control register r/w-0 u-0 r/w-1 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen ?cm ri to pd por bor bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16xxxx compatibility mode) bit 6 unimplemented: read as ? 0 ? bit 5 cm : configuration mismatch flag bit 1 = a configuration mismatch reset has not occurred 0 = a configuration mismatch reset occurred. must be set in software once the reset occurs. bit 4 ri : reset instruction flag bit 1 =the reset instruction was not executed (set by firmware only) 0 =the reset instruction was executed causing a device reset (must be set in software after a brown-out reset occurs) bit 3 to : watchdog time-out flag bit 1 = set by power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down detection flag bit 1 = set by power-up or by the clrwdt instruction 0 = set by execution of the sleep instruction bit 1 por : power-on reset status bit 1 = a power-on reset has not occurred (set by firmware only) 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = a brown-out reset has not occurred (set by firmware only) 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) note 1: it is recommended that the por bit be set after a power-on reset has been detected so that subsequent power-on resets may be detected. 2: if the on-chip voltage regulator is disabled, bor remains ? 0 ? at all times. see section 4.4.1 ?detecting bor? for more information. 3: brown-out reset is said to have occurred when bor is ? 0 ? and por is ? 1 ? (assuming that por was set to ? 1 ? by software immediately after a power-on reset). ? 2007 microchip technology inc. preliminary ds39774c-page 47 pic18f85j11 family 4.2 master clear (mclr ) the mclr pin provides a method for triggering a hard external reset of the device. a reset is generated by holding the pin low. pic18 extended microcontroller devices have a noise filter in the mclr reset path which detects and ignores small pulses. the mclr pin is not driven low by any internal resets, including the wdt. 4.3 power-on reset (por) a power-on reset condition is generated on-chip whenever v dd rises above a certain threshold. this allows the device to start in the initialized state when v dd is adequate for operation. to take advantage of the por circuitry, tie the mclr pin through a resistor (1 k to 10 k ) to v dd . this will eliminate external rc components usually needed to create a power-on reset delay. a minimum rise rate for v dd is specified (parameter d004). for a slow rise time, see figure 4-2. when the device starts normal operation (i.e., exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. power-on reset events are captured by the por bit (rcon<1>). the state of the bit is set to ? 0 ? whenever a power-on reset occurs; it does not change for any other reset event. por is not reset to ? 1 ? by any hardware event. to capture multiple events, the user manually resets the bit to ? 1 ? in software following any power-on reset. 4.4 brown-out reset (bor) the pic18f85j11 family of devices incorporates a simple bor function when the internal regulator is enabled (envreg pin is tied to v dd ). the voltage reg- ulator will trigger a brown-out reset when output of the regulator to the device core approaches the voltage at which the device is unable to run at full speed. the bor circuit also keeps the device in reset as v dd rises, until the regulator?s output level is sufficient for full-speed operation. once a bor has occurred, the power-up timer will keep the chip in reset for t pwrt (parameter 33). if v dd drops below the threshold for full-speed operation while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initialized. once v dd rises to the point where regulator output is sufficient, the power-up timer will execute the additional time delay. figure 4-2: external power-on reset circuit (for slow v dd power-up) 4.4.1 detecting bor the bor bit always resets to ? 0 ? on any brown-out reset or power-on reset event. this makes it difficult to determine if a brown-out reset event has occurred just by reading the state of bor alone. a more reliable method is to simultaneously check the state of both por and bor . this assumes that the por bit is reset to ? 1 ? in software immediately after any power-on reset event. if bor is ? 0 ? while por is ? 1 ?, it can be reliably assumed that a brown-out reset event has occurred. if the voltage regulator is disabled, brown-out reset functionality is disabled. in this case, the bor bit cannot be used to determine a brown-out reset event. the bor bit is still cleared by a power-on reset event. note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k is recommended to make sure that the voltage drop across r does not violate the device?s electrical specification. 3: r1 1 k will limit any current flowing into mclr from external capacitor c, in the event of mclr /v pp pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic18f85j11 v dd pic18f85j11 family ds39774c-page 48 preliminary ? 2007 microchip technology inc. 4.5 configuration mismatch (cm) the configuration mismatch (cm) reset is designed to detect and attempt to recover from random, memory corrupting events. these include electrostatic dis- charge (esd) events, which can cause widespread, single bit changes throughout the device and result in catastrophic failure. in pic18fxxjxx flash devices, the device configura- tion registers (located in the configuration memory space) are continuously monitored during operation by comparing their values to complimentary shadow registers. if a mismatch is detected between the two sets of reg- isters, a cm reset automatically occurs. these events are captured by the cm bit (rcon<5>) being set to ? 0 ?. this bit does not change for any other reset event. a cm reset behaves similarly to a master clear reset, reset instruction, wdt time-out or stack event resets. as with all hard and power reset events, the device configuration words are reloaded from the flash configuration words in program memory as the device restarts. 4.6 power-up timer (pwrt) pic18f85j11 family devices incorporate an on-chip power-up timer (pwrt) to help regulate the power-on reset process. the pwrt is always enabled. the main function is to ensure that the device voltage is stable before code is executed. the power-up timer (pwrt) of the pic18f85j11 fam- ily devices is an 11-bit counter which uses the intrc source as the clock input. this yields an approximate time interval of 2048 x 32 s = 65.6 ms. while the pwrt is counting, the device is held in reset. the power-up time delay depends on the intrc clock and will vary from chip-to-chip due to temperature and process variation. see dc parameter 33 for details. 4.6.1 time-out sequence if enabled, the pwrt time-out is invoked after the por pulse has cleared. the total time-out will vary based on the status of the pwrt. figure 4-3, figure 4-4, figure 4-5 and figure 4-6 all depict time-out sequences on power-up with the power-up timer enabled. since the time-outs occur from the por pulse, if mclr is kept low long enough, the pwrt will expire. bringing mclr high will begin execution immediately (figure 4-5). this is useful for testing purposes, or to synchronize more than one pic18fxxxx device operating in parallel. figure 4-3: time-out sequence on power-up (mclr tied to v dd , v dd rise < t pwrt ) t pwrt v dd mclr internal por pwrt time-out internal reset ? 2007 microchip technology inc. preliminary ds39774c-page 49 pic18f85j11 family figure 4-4: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 4-5: time-out sequence on power-up (mclr not tied to v dd ): case 2 figure 4-6: slow rise time (mclr tied to v dd , v dd rise > t pwrt ) t pwrt v dd mclr internal por pwrt time-out internal reset v dd mclr internal por pwrt time-out internal reset t pwrt v dd mclr internal por pwrt time-out internal reset 0v 1v 3.3v t pwrt pic18f85j11 family ds39774c-page 50 preliminary ? 2007 microchip technology inc. 4.7 reset state of registers most registers are unaffected by a reset. their status is unknown on por and unchanged by all other resets. the other registers are forced to a ?reset state? depending on the type of reset that occurred. most registers are not affected by a wdt wake-up, since this is viewed as the resumption of normal operation. status bits from the rcon register, cm , ri , to , pd , por and bor, are set or cleared differently in different reset situations, as indicated in table 4-1. these bits are used in software to determine the nature of the reset. table 4-2 describes the reset states for all of the special function registers. these are categorized by power-on and brown-out resets, master clear and wdt resets and wdt wake-ups. table 4-1: status bits, their significance and the initialization condition for rcon register condition program counter (1) rcon register stkptr register cm ri to pd por bor stkful stkunf power-on reset 0000h 111100 0 0 reset instruction 0000h u0uuuu u u brown-out reset 0000h 1111u0 u u mclr during power-managed run modes 0000h u u1uuu u u mclr during power-managed idle modes and sleep mode 0000h uu10uu u u wdt time-out during full power or power-managed run modes 0000h u u0uuu u u mclr during full power execution 0000h u uuuuu u u stack full reset (stvren = 1 ) 0000h u uuuuu 1 u stack underflow reset (stvren = 1 ) 0000h uuuuuu u 1 stack underflow error (not an actual reset, stvren = 0 ) 0000h uuuuuu u 1 wdt time-out during power-managed idle or sleep modes pc + 2 uu00uu u u interrupt exit from power-managed modes pc + 2 uuu0uu u u legend: u = unchanged note 1: when the wake-up is due to an interrupt and the gieh or giel bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). ? 2007 microchip technology inc. preliminary ds39774c-page 51 pic18f85j11 family table 4-2: initialization conditions for all registers register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets cm resets wake-up via wdt or interrupt tosu pic18f6xj11 pic18f8xj11 ---0 0000 ---0 0000 ---0 uuuu (1) tosh pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu (1) tosl pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu (1) stkptr pic18f6xj11 pic18f8xj11 uu-0 0000 00-0 0000 uu-u uuuu (1) pclatu pic18f6xj11 pic18f8xj11 ---0 0000 ---0 0000 ---u uuuu pclath pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu pcl pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 pc + 2 (2) tblptru pic18f6xj11 pic18f8xj11 --00 0000 --00 0000 --uu uuuu tblptrh pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu tblptrl pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu tablat pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu prodh pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu prodl pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu intcon pic18f6xj11 pic18f8xj11 0000 000x 0000 000u uuuu uuuu (3) intcon2 pic18f6xj11 pic18f8xj11 1111 1111 1111 1111 uuuu uuuu (3) intcon3 pic18f6xj11 pic18f8xj11 1100 0000 1100 0000 uuuu uuuu (3) indf0 pic18f6xj11 pic18f8xj11 n/a n/a n/a postinc0 pic18f6xj11 pic18f8xj11 n/a n/a n/a postdec0 pic18f6xj11 pic18f8xj11 n/a n/a n/a preinc0 pic18f6xj11 pic18f8xj11 n/a n/a n/a plusw0 pic18f6xj11 pic18f8xj11 n/a n/a n/a fsr0h pic18f6xj11 pic18f8xj11 ---- xxxx ---- uuuu ---- uuuu fsr0l pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu wreg pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu indf1 pic18f6xj11 pic18f8xj11 n/a n/a n/a postinc1 pic18f6xj11 pic18f8xj11 n/a n/a n/a postdec1 pic18f6xj11 pic18f8xj11 n/a n/a n/a preinc1 pic18f6xj11 pic18f8xj11 n/a n/a n/a plusw1 pic18f6xj11 pic18f8xj11 n/a n/a n/a legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 4-1 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read as ? 0 ?. pic18f85j11 family ds39774c-page 52 preliminary ? 2007 microchip technology inc. fsr1h pic18f6xj11 pic18f8xj11 ---- xxxx ---- uuuu ---- uuuu fsr1l pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu bsr pic18f6xj11 pic18f8xj11 ---- 0000 ---- 0000 ---- uuuu indf2 pic18f6xj11 pic18f8xj11 n/a n/a n/a postinc2 pic18f6xj11 pic18f8xj11 n/a n/a n/a postdec2 pic18f6xj11 pic18f8xj11 n/a n/a n/a preinc2 pic18f6xj11 pic18f8xj11 n/a n/a n/a plusw2 pic18f6xj11 pic18f8xj11 n/a n/a n/a fsr2h pic18f6xj11 pic18f8xj11 ---- xxxx ---- uuuu ---- uuuu fsr2l pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu status pic18f6xj11 pic18f8xj11 ---x xxxx ---u uuuu ---u uuuu tmr0h pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu tmr0l pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu t0con pic18f6xj11 pic18f8xj11 1111 1111 1111 1111 uuuu uuuu osccon pic18f6xj11 pic18f8xj11 0100 q000 0100 q000 uuuu quuu wdtcon pic18f6xj11 pic18f8xj11 0--- ---0 0--- ---0 u--- ---u rcon (4) pic18f6xj11 pic18f8xj11 0-11 11q0 0-uq qquu u-uu qquu tmr1h pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu tmr1l pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu t1con pic18f6xj11 pic18f8xj11 0000 0000 u0uu uuuu uuuu uuuu tmr2 pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu pr2 pic18f6xj11 pic18f8xj11 1111 1111 1111 1111 1111 1111 t2con pic18f6xj11 pic18f8xj11 -000 0000 -000 0000 -uuu uuuu sspbuf pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu sspadd pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu sspstat pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu sspcon1 pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu sspcon2 pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu table 4-2: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets cm resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 4-1 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read as ? 0 ?. ? 2007 microchip technology inc. preliminary ds39774c-page 53 pic18f85j11 family adresh pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu adresl pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu adcon0 pic18f6xj11 pic18f8xj11 0-00 0000 0-00 0000 u-uu uuuu adcon1 pic18f6xj11 pic18f8xj11 --00 0000 --00 0000 --uu uuuu adcon2 pic18f6xj11 pic18f8xj11 0-00 0000 0-00 0000 u-uu uuuu cvrcon pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu cmcon pic18f6xj11 pic18f8xj11 0000 0111 0000 0111 uuuu uuuu tmr3h pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu tmr3l pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu t3con pic18f6xj11 pic18f8xj11 0000 0000 uuuu uuuu uuuu uuuu pspcon pic18f6xj11 pic18f8xj11 0000 ---- 0000 ---- uuuu ---- spbrg1 pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu rcreg1 pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu txreg1 pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu txsta1 pic18f6xj11 pic18f8xj11 0000 0010 0000 0010 uuuu uuuu rcsta1 pic18f6xj11 pic18f8xj11 0000 000x 0000 000x uuuu uuuu eecon2 pic18f6xj11 pic18f8xj11 ---- ---- ---- ---- ---- ---- eecon1 pic18f6xj11 pic18f8xj11 ---0 x00- ---0 u00- ---0 u00- ipr3 pic18f6xj11 pic18f8xj11 --00 -11- --00 -11- --uu -uu- pir3 pic18f6xj11 pic18f8xj11 --00 -00- --00 -00- --uu -00- (3) pie3 pic18f6xj11 pic18f8xj11 --00 -00- --00 -00- --uu -00- ipr2 pic18f6xj11 pic18f8xj11 11-- 111- 11-- 111- uu-- uuu- pir2 pic18f6xj11 pic18f8xj11 00-- 000- 00-- 000- uu-- uuu- (3) pie2 pic18f6xj11 pic18f8xj11 00-- 000- 00-- 000- uu-- uuu- ipr1 pic18f6xj11 pic18f8xj11 1111 1-11 1111 1-11 uuuu u-uu pir1 pic18f6xj11 pic18f8xj11 0000 0-00 0000 0-00 uuuu u-uu (3) pie1 pic18f6xj11 pic18f8xj11 0000 0-00 0000 0-00 uuuu u-uu memcon pic18f6xj11 pic18f8xj11 0-00 --00 0-00 --00 u-uu --uu osctune pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu table 4-2: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets cm resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 4-1 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read as ? 0 ?. pic18f85j11 family ds39774c-page 54 preliminary ? 2007 microchip technology inc. trisj pic18f6xj11 pic18f8xj11 1111 1111 1111 1111 uuuu uuuu trish pic18f6xj11 pic18f8xj11 1111 1111 1111 1111 uuuu uuuu trisg pic18f6xj11 pic18f8xj11 0001 1111 0001 1111 uuuu uuuu trisf pic18f6xj11 pic18f8xj11 1111 111- 1111 111- uuuu uuu- trise pic18f6xj11 pic18f8xj11 1111 1-11 1111 1-11 uuuu u-uu trisd pic18f6xj11 pic18f8xj11 1111 1111 1111 1111 uuuu uuuu trisc pic18f6xj11 pic18f8xj11 1111 1111 1111 1111 uuuu uuuu trisb pic18f6xj11 pic18f8xj11 1111 1111 1111 1111 uuuu uuuu trisa (5) pic18f6xj11 pic18f8xj11 1111 1111 (5) 1111 1111 (5) uuuu uuuu (5) latj pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu lath pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu latg pic18f6xj11 pic18f8xj11 00-x xxxx 00-u uuuu uu-u uuuu latf pic18f6xj11 pic18f8xj11 xxxx xxx- uuuu uuu- uuuu uuu- late pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu latd pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu latc pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu latb pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu lata (5) pic18f6xj11 pic18f8xj11 xxxx xxxx (5) uuuu uuuu (5) uuuu uuuu (5) portj pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu porth pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu portg pic18f6xj11 pic18f8xj11 000x xxxx 000u uuuu 000u uuuu portf pic18f6xj11 pic18f8xj11 xxxx xxx- uuuu uuu- uuuu uuu- porte pic18f6xj11 pic18f8xj11 xxxx x-xx uuuu u-uu uuuu u-uu portd pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu portc pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu portb pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu porta (5) pic18f6xj11 pic18f8xj11 xx0x 0000 (5) uu0u 0000 (5) uuuu uuuu (5) spbrgh1 pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu baudcon1 pic18f6xj11 pic18f8xj11 01-0 0-00 01-0 0-00 uu-u u-uu ccpr1h pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu ccpr1l pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu ccp1con pic18f6xj11 pic18f8xj11 --00 0000 --00 0000 --uu uuuu table 4-2: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets cm resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 4-1 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read as ? 0 ?. ? 2007 microchip technology inc. preliminary ds39774c-page 55 pic18f85j11 family ccpr2h pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu ccpr2l pic18f6xj11 pic18f8xj11 xxxx xxxx uuuu uuuu uuuu uuuu ccp2con pic18f6xj11 pic18f8xj11 --00 0000 --00 0000 --uu uuuu spbrg2 pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu rcreg2 pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu txreg2 pic18f6xj11 pic18f8xj11 0000 0000 0000 0000 uuuu uuuu txsta2 pic18f6xj11 pic18f8xj11 0000 -010 0000 -010 uuuu -uuu rcsta2 pic18f6xj11 pic18f8xj11 0000 000x 0000 000x uuuu uuuu table 4-2: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets cm resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 4-1 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read as ? 0 ?. pic18f85j11 family ds39774c-page 56 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. preliminary ds39774c-page 57 pic18f85j11 family 5.0 memory organization there are two types of memory in pic18 flash microcontroller devices: ? program memory ? data ram as harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. additional detailed information on the operation of the flash program memory is provided in section 6.0 ?flash program memory? . 5.1 program memory organization pic18 microcontrollers implement a 21-bit program counter which is capable of addressing a 2-mbyte program memory space. accessing a location between the upper boundary of the physically implemented memory and the 2-mbyte address will return all ? 0 ?s (a nop instruction). the entire pic18f85j11 family offers a range of on-chip flash program memory sizes, from 8 kbytes (up to 4,096 single-word instructions) to 32 kbytes (32,768 single-word instructions). the program memory maps for individual family members are shown in figure 5-1. figure 5-1: memory maps for pic18f85j11 family devices note: sizes of memory areas are not to scale. sizes of program memory areas are enhanced to show detail. unimplemented read as ? 0 ? unimplemented read as ? 0 ? unimplemented read as ? 0 ? 000000h 1fffffh 007fffh pic18fx3j11 pic18fx4j11 pic18fx5j11 001fffh 003fffh pc<20:0> stack level 1 ? stack level 31 ? ? call, callw, rcall, return, retfie, retlw, 21 user memory space on-chip memory on-chip memory on-chip memory addulnk, subulnk config. words config. words config. words pic18f85j11 family ds39774c-page 58 preliminary ? 2007 microchip technology inc. 5.1.1 hard memory vectors all pic18 devices have a total of three hard-coded return vectors in their program memory space. the reset vector address is the default value to which the program counter returns on all device resets; it is located at 0000h. pic18 devices also have two interrupt vector addresses for the handling of high priority and low priority interrupts. the high priority interrupt vector is located at 0008h and the low priority interrupt vector is at 0018h. their locations in relation to the program memory map are shown in figure 5-2. figure 5-2: hard vector and configuration word locations for pic18f85j11 family family devices 5.1.2 flash configuration words because pic18f85j11 family devices do not have per- sistent configuration memory, the top four words of on-chip program memory are reserved for configuration information. on reset, the configuration information is copied into the configuration registers. the configuration words are stored in their program memory location in numerical order, starting with the lower byte of config1 at the lowest address and end- ing with the upper byte of config4. for these devices, only configuration words, config1 through config3, are used; config4 is reserved. the actual addresses of the flash configuration word for devices in the pic18f85j11 family are shown in table 5-1. their location in the memory map is shown with the other memory vectors in figure 5-2. additional details on the device configuration words are provided in section 22.1 ?configuration bits? . table 5-1: flash configuration word for pic18f85j11 family devices reset vector low priority interrupt vector 0000h 0018h on-chip program memory high priority interrupt vector 0008h 1fffffh (top of memory) (top of memory-7) flash configuration words read as ? 0 ? legend: (top of memory) represents upper boundary of on-chip program memory space (see figure 5-1 for device-specific values). shaded area represents unimplemented memory. areas are not shown to scale. device program memory (kbytes) configuration word addresses pic18f63j11 8 1ff8h to 1fffh pic18f83j11 pic18f64j11 16 3ff8h to 3fffh pic18f84j11 pic18f65j11 32 7ff8h to 7fffh pic18f85j11 ? 2007 microchip technology inc. preliminary ds39774c-page 59 pic18f85j11 family 5.1.3 pic18f8xj11 program memory modes the 80-pin devices in this family can address up to a total of 2 mbytes of program memory. this is achieved through the external memory bus. there are two distinct operating modes available to the controllers: ? microcontroller (mc) ? extended microcontroller (emc) the program memory mode is determined by setting the emb configuration bits (config3l<5:4>), as shown in register 5-1. (see also section 22.1 ?configuration bits? for additional details on the device configuration bits.) the program memory modes operate as follows: ?the microcontroller mode accesses only on-chip flash memory. attempts to read above the top of on-chip memory causes a read of all ? 0 ?s (a nop instruction). the microcontroller mode is also the only operating mode available to 64-pin devices. ?the extended microcontroller mode allows access to both internal and external program memories as a single block. the device can access its entire on-chip program memory; above this, the device accesses external program memory up to the 2-mbyte program space limit. execution automatically switches between the two memories as required. the setting of the emb configuration bits also controls the address bus width of the external memory bus. this is covered in more detail in section 7.0 ?external memory bus? . in all modes, the microcontroller has complete access to data ram. figure 5-3 compares the memory maps of the different program memory modes. the differences between on-chip and external memory access limitations are more fully explained in table 5-2. register 5-1: config3l: configuration register 3 low (byte address 300004h) (1) r/wo-1 r/wo-1 r/wo-1 r/wo-1 r/wo-1 u-0 u-0 u-0 wait bw emb1 emb0 eashft ? ? ? bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as ? 0 ? -n = value when device is unprogrammed ?1? = bit is set ?0? = bit is cleared bit 7 wait: external bus wait enable bit 1 = wait selections from memcon.wait<1:0> unavailable, and the device will not wait 0 = wait programmed by memcon.wait<1:0> bit 6 bw: data bus width select bit 1 = 16-bit external bus mode 0 = 8-bit external bus mode bit 5:4 emb1:emb0: external memory bus configuration bits 00 = extended microcontroller mode ? 20-bit address mode 01 = extended microcontroller mode ? 16-bit address mode 10 = extended microcontroller mode ? 12-bit address mode 11 = microcontroller mode ? external bus disabled bit 3 eashft: external address bus shift enable bit 1 = address shifting enabled ? external address bus is shifted to start at 000000h 0 = address shifting disabled ? external address bus reflects the pc value bit 2-0 unimplemented: read as ? 0 ? note 1: config3l and its associated bits are implemented only in 80-pin devices. pic18f85j11 family ds39774c-page 60 preliminary ? 2007 microchip technology inc. 5.1.4 extended microcontroller mode and address shifting by default, devices in extended microcontroller mode directly present the program counter value on the external address bus for those addresses in the range of the external memory space. in practical terms, this means addresses in the external memory device below the top of on-chip memory are unavailable. to avoid this, the extended microcontroller mode implements an address shifting option to enable auto- matic address translation. in this mode, addresses presented on the external bus are shifted down by the size of the on-chip program memory and are remapped to start at 0000h. this allows the complete use of the external memory device?s memory space. figure 5-3: memory maps for pic18f85j11 family program memory modes table 5-2: memory access for pic18f 8xj11 program memory modes external memory on-chip program memory microcontroller mode (1) 000000h on-chip program memory 1fffffh reads ? 0 ?s external on-chip memory memory (top of memory) (top of memory) + 1 legend: (top of memory) represents upper boundary of on-chip program memory space (see figure 5-1 for device-specific values). shaded areas represent unimplement ed, or inaccessible areas, depending on the mode. note 1: this mode is the only available mode on 64 -pin devices and the default on 80-pin devices. 2: these modes are only ava ilable on 80-pin devices. extended microcontroller mode (2) 000000h 1fffffh (top of memory) (top of memory) + 1 external memory on-chip program memory 000000h 1fffffh (top of memory) (top of memory) + 1 no access space on-chip memory space external on-chip memory memory space mapped to external memory space space space mapped to external memory space (top of memory) extended microcontroller mode with address shifting (2) 1fffffh ? operating mode internal program memory external program memory execution from table read from table write to execution from table read from table write to microcontroller yes yes yes no access no access no access extended microcontroller yes yes yes yes yes yes ? 2007 microchip technology inc. preliminary ds39774c-page 61 pic18f85j11 family 5.1.5 program counter the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 21 bits wide and is contained in three separate 8-bit registers. the low byte, known as the pcl register, is both readable and writable. the high byte, or pch register, contains the pc<15:8> bits; it is not directly readable or writable. updates to the pch register are performed through the pclath register. the upper byte is called pcu. this register contains the pc<20:16> bits; it is also not directly readable or writable. updates to the pcu register are performed through the pclatu register. the contents of pclath and pclatu are transferred to the program counter by any operation that writes pcl. similarly, the upper two bytes of the program counter are transferred to pclath and pclatu by an operation that reads pcl. this is useful for computed offsets to the pc (see section 5.1.8.1 ?computed goto? ). the pc addresses bytes in the program memory. to prevent the pc from becoming misaligned with word instructions, the least significant bit of pcl is fixed to a value of ? 0 ?. the pc increments by 2 to address sequential instructions in the program memory. the call , rcall , goto and program branch instructions write to the program counter directly. for these instructions, the contents of pclath and pclatu are not transferred to the program counter. 5.1.6 return address stack the return address stack allows any combination of up to 31 program calls and interrupts to occur. the pc is pushed onto the stack when a call or rcall instruc- tion is executed, or an interrupt is acknowledged. the pc value is pulled off the stack on a return , retlw or a retfie instruction (and on addulnk and subulnk instructions if the extended instruction set is enabled). pclatu and pclath are not affected by any of the return or call instructions. the stack operates as a 31-word by 21-bit ram and a 5-bit stack pointer, stkptr. the stack space is not part of either program or data space. the stack pointer is readable and writable and the address on the top of the stack is readable and writable through the top-of-stack special function registers. data can also be pushed to, or popped from the stack, using these registers. a call type instruction causes a push onto the stack. the stack pointer is first incremented and the location pointed to by the stack pointer is written with the contents of the pc (already pointing to the instruction following the call ). a return type instruction causes a pop from the stack. the contents of the location pointed to by the stkptr are transferred to the pc and then the stack pointer is decremented. the stack pointer is initialized to ? 00000 ? after all resets. there is no ram associated with the location corresponding to a stack pointer value of ? 00000 ?; this is only a reset value. status bits indicate if the stack is full, has overflowed or has underflowed. 5.1.6.1 top-of-stack access only the top of the return address stack (tos) is readable and writable. a set of three registers, tosu:tosh:tosl, holds the contents of the stack location pointed to by the stkptr register (figure 5-4). this allows users to implement a software stack if necessary. after a call , rcall or interrupt (and addulnk and subulnk instructions if the extended instruction set is enabled), the software can read the pushed value by reading the tosu:tosh:tosl registers. these values can be placed on a user-defined software stack. at return time, the software can return these values to tosu:tosh:tosl and do a return. the user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. figure 5-4: return address stack and associated registers 00011 001a34h 11111 11110 11101 00010 00001 00000 00010 return address stack <20:0> top-of-stack 000d58h tosl tosh tosu 34h 1ah 00h stkptr<4:0> top-of-stack registers stack pointer pic18f85j11 family ds39774c-page 62 preliminary ? 2007 microchip technology inc. 5.1.6.2 return stack pointer (stkptr) the stkptr register (register 5-2) contains the stack pointer value, the stkful (stack full) status bit and the stkunf (stack underflow) status bits. the value of the stack pointer can be 0 through 31. the stack pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. on reset, the stack pointer value will be zero. the user may read and write the stack pointer value. this feature can be used by a real-time operating system (rtos) for return stack maintenance. after the pc is pushed onto the stack 31 times (without popping any values off the stack), the stkful bit is set. the stkful bit is cleared by software or by a por. the action that takes place when the stack becomes full depends on the state of the stvren (stack over- flow reset enable) configuration bit. (refer to section 22.1 ?configuration bits? for a description of the device configuration bits.) if stvren is set (default), the 31st push will push the (pc + 2) value onto the stack, set the stkful bit and reset the device. the stkful bit will remain set and the stack pointer will be set to zero. if stvren is cleared, the stkful bit will be set on the 31st push and the stack pointer will increment to 31. any additional pushes will not overwrite the 31st push and the stkptr will remain at 31. when the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the pc and set the stkunf bit, while the stack pointer remains at zero. the stkunf bit will remain set until cleared by software or until a por occurs. 5.1.6.3 push and pop instructions since the top-of-stack is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execu- tion, is a desirable feature. the pic18 instruction set includes two instructions, push and pop , that permit the tos to be manipulated under software control. tosu, tosh and tosl can be modified to place data or a return address on the stack. the push instruction places the current pc value onto the stack. this increments the stack pointer and loads the current pc value onto the stack. the pop instruction discards the current tos by decrementing the stack pointer. the previous value pushed onto the stack then becomes the tos value. note: returning a value of zero to the pc on an underflow has the effect of vectoring the program to the reset vector, where the stack conditions can be verified and appropriate actions can be taken. this is not the same as a reset, as the contents of the sfrs are not affected. register 5-2: stkptr: stack pointer register r/c-0 r/c-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stkful (1) stkunf (1) ? sp4 sp3 sp2 sp1 sp0 bit 7 bit 0 legend: c = clearable-only bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 stkful: stack full flag bit (1) 1 = stack became full or overflowed 0 = stack has not become full or overflowed bit 6 stkunf: stack underflow flag bit (1) 1 = stack underflow occurred 0 = stack underflow did not occur bit 5 unimplemented: read as ? 0 ? bit 4-0 sp4:sp0: stack pointer location bits note 1: bit 7 and bit 6 are cleared by user software or by a por. ? 2007 microchip technology inc. preliminary ds39774c-page 63 pic18f85j11 family 5.1.6.4 stack full and underflow resets device resets on stack overflow and stack underflow conditions are enabled by setting the stvren bit in configuration register 1l. when stvren is set, a full or underflow condition will set the appropriate stkful or stkunf bit and then cause a device reset. when stvren is cleared, a full or underflow condition will set the appropriate stkful or stkunf bit, but not cause a device reset. the stkful or stkunf bits are cleared by the user software or a power-on reset. 5.1.7 fast register stack a fast register stack is provided for the status, wreg and bsr registers to provide a ?fast return? option for interrupts. this stack is only one level deep and is neither readable nor writable. it is loaded with the current value of the corresponding register when the processor vectors for an interrupt. all interrupt sources will push values into the stack registers. the values in the registers are then loaded back into the working registers if the retfie, fast instruction is used to return from the interrupt. if both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. if a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. in these cases, users must save the key registers in software during a low priority interrupt. if interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. if no interrupts are used, the fast register stack can be used to restore the status, wreg and bsr registers at the end of a subroutine call. to use the fast register stack for a subroutine call, a call label, fast instruction must be executed to save the status, wreg and bsr registers to the fast register stack. a return, fast instruction is then executed to restore these registers from the fast register stack. example 5-1 shows a source code example that uses the fast register stack during a subroutine call and return. example 5-1: fast register stack code example 5.1.8 look-up tables in program memory there may be programming situations that require the creation of data structures, or look-up tables, in program memory. for pic18 devices, look-up tables can be implemented in two ways: ? computed goto ? table reads 5.1.8.1 computed goto a computed goto is accomplished by adding an offset to the program counter. an example is shown in example 5-2. a look-up table can be formed with an addwf pcl instruction and a group of retlw nn instructions. the w register is loaded with an offset into the table before executing a call to that table. the first instruction of the called routine is the addwf pcl instruction. the next instruction executed will be one of the retlw nn instructions that returns the value ? nn ? to the calling function. the offset value (in wreg) specifies the number of bytes that the program counter should advance and should be multiples of 2 (lsb = 0 ). in this method, only one data byte may be stored in each instruction location and room on the return address stack is required. example 5-2: computed goto using an offset value 5.1.8.2 table reads a better method of storing data in program memory allows two bytes of data to be stored in each instruction location. look-up table data may be stored two bytes per program word while programming. the table pointer (tblptr) specifies the byte address and the table latch (tablat) contains the data that is read from the program memory. data is transferred from program memory one byte at a time. table read operation is discussed further in section 6.1 ?table reads and table writes? . call sub1, fast ;status, wreg, bsr ;saved in fast register ;stack ? ? sub1 ? ? return fast ;restore values saved ;in fast register stack movf offset, w call table org nn00h table addwf pcl retlw nnh retlw nnh retlw nnh . . . pic18f85j11 family ds39774c-page 64 preliminary ? 2007 microchip technology inc. 5.2 pic18 instruction cycle 5.2.1 clocking scheme the microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (q1, q2, q3 and q4). internally, the program counter is incremented on every q1; the instruction is fetched from the program memory and latched into the instruction register (ir) during q4. the instruction is decoded and executed during the following q1 through q4. the clocks and instruction execution flow are shown in figure 5-5. 5.2.2 instruction flow/pipelining an ?instruction cycle? consists of four q cycles, q1 through q4. the instruction fetch and execute are pipe- lined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), then two cycles are required to complete the instruction (example 5-3). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 5-5: clock/ instruction cycle example 5-3: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clko (rc mode) pc pc + 2 pc + 4 fetch inst (pc) execute inst (pc ? 2) fetch inst (pc + 2) execute inst (pc) fetch inst (pc + 4) execute inst (pc + 2) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ?flushed? from the pipeline while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. bra sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush ( nop ) 5. instruction @ address sub_1 fetch sub_1 execute sub_1 ? 2007 microchip technology inc. preliminary ds39774c-page 65 pic18f85j11 family 5.2.3 instructions in program memory the program memory is addressed in bytes. instruc- tions are stored as two bytes or four bytes in program memory. the least significant byte of an instruction word is always stored in a program memory location with an even address (lsb = 0 ). to maintain alignment with instruction boundaries, the pc increments in steps of 2 and the lsb will always read ? 0 ? (see section 5.1.5 ?program counter? ). figure 5-6 shows an example of how instruction words are stored in the program memory. the call and goto instructions have the absolute program memory address embedded into the instruc- tion. since instructions are always stored on word boundaries, the data contained in the instruction is a word address. the word address is written to pc<20:1> which accesses the desired byte address in program memory. instruction #2 in figure 5-6 shows how the instruction, goto 0006h , is encoded in the program memory. program branch instructions, which encode a relative address offset, operate in the same manner. the offset value stored in a br anch instruction represents the number of single-word instructions that the pc will be offset by. section 23.0 ?instruction set summary? provides further details of the instruction set. figure 5-6: instructions in program memory 5.2.4 two-word instructions the standard pic18 instruction set has four two-word instructions: call , movff , goto and lsfr . in all cases, the second word of the instructions always has ? 1111 ? as its four most significant bits; the other 12 bits are literal data, usually a data memory address. the use of ? 1111 ? in the 4 msbs of an instruction specifies a special form of nop . if the instruction is executed in proper sequence ? immediately after the first word ? the data in the second word is accessed and used by the instruction sequence. if the first word is skipped for some reason and the second word is executed by itself, a nop is executed instead. this is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the pc. example 5-4 shows how this works. example 5-4: two-word instructions word address lsb = 1 lsb = 0 program memory byte locations 000000h 000002h 000004h 000006h instruction 1: movlw 055h 0fh 55h 000008h instruction 2: goto 0006h efh 03h 00000ah f0h 00h 00000ch instruction 3: movff 123h, 456h c1h 23h 00000eh f4h 56h 000010h 000012h 000014h note: see section 5.5 ?program memory and the extended instruction set? for information on two-word instructions in the extended instruction set. case 1: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; no, skip this word 1111 0100 0101 0110 ; execute this word as a nop 0010 0100 0000 0000 addwf reg3 ; continue code case 2: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 addwf reg3 ; continue code pic18f85j11 family ds39774c-page 66 preliminary ? 2007 microchip technology inc. 5.3 data memory organization the data memory in pic18 devices is implemented as static ram. each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. the memory space is divided into as many as 16 banks that contain 256 bytes each. the pic18fx3j11/x4j11 devices, with up to 16 kbytes of program memory, implement 4 complete banks for a total of 1024 bytes. pic18fx5j11 devices, with 32 kbytes of program memory, implement 8 complete banks for a total of 2048 bytes. figure 5-7 and figure 5-8 show the data memory organization for the devices. the data memory contains special function registers (sfrs) and general purpose registers (gprs). the sfrs are used for control and status of the controller and peripheral functions, while gprs are used for data storage and scratchpad operations in the user?s application. any read of an unimplemented location will read as ? 0 ?s. the instruction set and architecture allow operations across all banks. the entire data memory may be accessed by direct, indirect or indexed addressing modes. addressing modes are discussed later in this section. to ensure that commonly used registers (select sfrs and select gprs) can be accessed in a single cycle, pic18 devices implement an access bank. this is a 256-byte memory space that provides fast access to select sfrs and the lower portion of gpr bank 0 with- out using the bsr. section 5.3.2 ?access bank? provides a detailed description of the access ram. 5.3.1 bank select register large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. ideally, this means that an entire address does not need to be provided for each read or write operation. for pic18 devices, this is accom- plished with a ram banking scheme. this divides the memory space into 16 contiguous banks of 256 bytes. depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit bank pointer. most instructions in the pic18 instruction set make use of the bank pointer, known as the bank select register (bsr). this sfr holds the 4 most significant bits of a location?s address; the instruction itself includes the 8 least significant bits. only the four lower bits of the bsr are implemented (bsr3:bsr0). the upper four bits are unused; they will always read ? 0 ? and cannot be written to. the bsr can be loaded directly by using the movlb instruction. the value of the bsr indicates the bank in data memory. the 8 bits in the instruction show the location in the bank and can be thought of as an offset from the bank?s lower boundary. the relationship between the bsr?s value and the bank division in data memory is shown in figure 5-9. since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. for example, writing what should be program data to an 8-bit address of f9h while the bsr is 0fh, will end up resetting the program counter. while any bank can be selected, only those banks that are actually implemented can be read or written to. writes to unimplemented banks are ignored, while reads from unimplemented banks will return ? 0 ?s. even so, the status register will still be affected as if the operation was successful. the data memory map in figure 5-7 indicates which banks are implemented. in the core pic18 instruction set, only the movff instruction fully specifies the 12-bit address of the source and target registers. this instruction ignores the bsr completely when it executes. all other instructions include only the low-order address as an operand and must use either the bsr or the access bank to locate their target registers. note: the operation of some aspects of data memory are changed when the pic18 extended instruction set is enabled. see section 5.6 ?data memory and the extended instruction set? for more information. ? 2007 microchip technology inc. preliminary ds39774c-page 67 pic18f85j11 family figure 5-7: data memory map for pic18fx3j11/x4j11 devices 00h 5fh 60h ffh access bank when a = 0 : the bsr is ignored and the access bank is used. the first 96 bytes are general purpose ram (from bank 0). the second 160 bytes are special function registers (from bank 15). when a = 1 : the bsr specifies the bank used by the instruction. access ram high access ram low (sfrs) bank 0 bank 1 bank 14 bank 15 data memory map bsr<3:0> = 0000 = 0001 = 1111 060h 05fh f60h fffh f5fh f00h effh 1ffh 100h 0ffh 000h access ram ffh 00h ffh 00h ffh 00h gpr gpr sfr bank 2 = 0010 2ffh 200h bank 3 ffh 00h gpr ffh = 0011 unused gpr 400h 3ffh 300h ffh 00h 00h = 0100 bank 4 = 1110 to unused read as ? 0 ? pic18f85j11 family ds39774c-page 68 preliminary ? 2007 microchip technology inc. figure 5-8: data memory map for pic18fx5j11 devices 00h 5fh 60h ffh access bank when a = 0 : the bsr is ignored and the access bank is used. the first 96 bytes are general purpose ram (from bank 0). the second 160 bytes are special function registers (from bank 15). when a = 1 : the bsr specifies the bank used by the instruction. access ram high access ram low (sfrs) bank 0 bank 1 bank 14 bank 15 data memory map bsr<3:0> = 0000 = 0001 = 1111 060h 05fh f60h fffh f5fh f00h effh 1ffh 100h 0ffh 000h access ram ffh 00h ffh 00h ffh 00h gpr gpr sfr bank 2 = 0010 2ffh 200h bank 3 ffh 00h gpr ffh = 0011 unused gpr gpr gpr gpr gpr 4ffh 400h 5ffh 500h 3ffh 300h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h 00h = 0110 = 0111 = 1000 = 0101 = 0100 bank 4 bank 5 bank 6 bank 7 bank 8 = 1110 6ffh 600h 7ffh 700h 800h to unused read as ? 0 ? ? 2007 microchip technology inc. preliminary ds39774c-page 69 pic18f85j11 family figure 5-9: use of the bank select register (direct addressing) 5.3.2 access bank while the use of the bsr with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. otherwise, data may be read from, or written to, the wrong location. this can be disastrous if a gpr is the intended target of an oper- ation, but an sfr is written to instead. verifying and/or changing the bsr for each read or write to data memory can become very inefficient. to streamline access for the most commonly used data memory locations, the data memory is configured with an access bank, which allows users to access a mapped block of memory without specifying a bsr. the access bank consists of the first 96 bytes of memory (00h-5fh) in bank 0 and the last 160 bytes of memory (60h-ffh) in bank 15. the lower half is known as the ?access ram? and is composed of gprs. the upper half is where the device?s sfrs are mapped. these two areas are mapped contiguously in the access bank and can be addressed in a linear fashion by an 8-bit address (figure 5-7). the access bank is used by core pic18 instructions that include the access ram bit (the ?a? parameter in the instruction). when ?a? is equal to ? 1 ?, the instruction uses the bsr and the 8-bit address included in the opcode for the data memory address. when ?a? is ? 0 ?, however, the instruction is forced to use the access bank address map; the current value of the bsr is ignored entirely. using this ?forced? addressing allows the instruction to operate on a data address in a single cycle without updating the bsr first. for 8-bit addresses of 60h and above, this means that users can evaluate and operate on sfrs more efficiently. the access ram below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. access ram also allows for faster and more code efficient context saving and switching of variables. the mapping of the access bank is slightly different when the extended instruction set is enabled (xinst configuration bit = 1 ). this is discussed in more detail in section 5.6.3 ?mapping the access bank in indexed literal offset mode? . 5.3.3 general purpose register file pic18 devices may have banked memory in the gpr area. this is data ram which is available for use by all instructions. gprs start at the bottom of bank 0 (address 000h) and grow upwards towards the bottom of the sfr area. gprs are not initialized by a power-on reset and are unchanged on all other resets. note 1: the access ram bit of the instruction can be used to force an override of the selected bank (bsr<3:0>) to the registers of the access bank. 2: the movff instruction embeds the entire 12-bit address in the instruction. data memory bank select (2) 7 0 from opcode (2) 0000 000h 100h 200h 300h f00h e00h fffh bank 0 bank 1 bank 2 bank 14 bank 15 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh bank 3 through bank 13 0010 11111111 7 0 bsr (1) 11111111 pic18f85j11 family ds39774c-page 70 preliminary ? 2007 microchip technology inc. 5.3.4 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. sfrs start at the top of data memory (fffh) and extend downward to occupy more than the top half of bank 15 (f60h to fffh). a list of these registers is given in table 5-3 and table 5-4. the sfrs can be classified into two sets: those associated with the ?core? device functionality (alu, resets and interrupts) and those related to the peripheral functions. the reset and interrupt registers are described in their respective chapters, while the alu?s status register is described later in this section. registers related to the operation of the peripheral features are described in t he chapter for that peripheral. the sfrs are typically distributed among the peripherals whose functions they control. unused sfr locations are unimplemented and read as ? 0 ?s. table 5-3: special function register map for pic18f85j11 family devices address name address name address name address name address name fffh tosu fdfh indf2 (1) fbfh ? (2) f9fh ipr1 f7fh spbrgh1 ffeh tosh fdeh postinc2 (1) fbeh ? (2) f9eh pir1 f7eh baudcon1 ffdh tosl fddh postdec2 (1) fbdh ? (2) f9dh pie1 f7dh ? (2) ffch stkptr fdch preinc2 (1) fbch ? (2) f9ch memcon (3) f7ch ? (2) ffbh pclatu fdbh plusw2 (1) fbbh ? (2) f9bh osctune f7bh ? (2) ffah pclath fdah fsr2h fbah ? (2) f9ah trisj (3) f7ah ? (2) ff9h pcl fd9h fsr2l fb9h ? (2) f99h trish (3) f79h ? (2) ff8h tblptru fd8h status fb8h ? (2) f98h trisg f78h ? (2) ff7h tblptrh fd7h tmr0h fb7h ? (2) f97h trisf f77h ? (2) ff6h tblptrl fd6h tmr0l fb6h ? (2) f96h trise f76h ? (2) ff5h tablat fd5h t0con fb5h cvrcon f95h trisd f75h ? (2) ff4h prodh fd4h ? (2) fb4h cmcon f94h trisc f74h ? (2) ff3h prodl fd3h osccon fb3h tmr3h f93h trisb f73h ? (2) ff2h intcon fd2h ? (2) fb2h tmr3l f92h trisa f72h ? (2) ff1h intcon2 fd1h wdtcon fb1h t3con f91h latj (3) f71h ? (2) ff0h intcon3 fd0h rcon fb0h pspcon f90h lath (3) f70h ? (2) fefh indf0 (1) fcfh tmr1h fafh spbrg1 f8fh latg f6fh ? (2) feeh postinc0 (1) fceh tmr1l faeh rcreg1 f8eh latf f6eh ? (2) fedh postdec0 (1) fcdh t1con fadh txreg1 f8dh late f6dh ? (2) fech preinc0 (1) fcch tmr2 fach txsta1 f8ch latd f6ch ? (2) febh plusw0 (1) fcbh pr2 fabh rcsta1 f8bh latc f6bh ? (2) feah fsr0h fcah t2con faah ? (2) f8ah latb f6ah ccpr1h fe9h fsr0l fc9h sspbuf fa9h ? (2) f89h lata f69h ccpr1l fe8h wreg fc8h sspadd fa8h ? (2) f88h portj (3) f68h ccp1con fe7h indf1 (1) fc7h sspstat fa7h eecon2 f87h porth (3) f67h ccpr2h fe6h postinc1 (1) fc6h sspcon1 fa6h eecon1 f86h portg f66h ccpr2l fe5h postdec1 (1) fc5h sspcon2 fa5h ipr3 f85h portf f65h ccp2con fe4h preinc1 (1) fc4h adresh fa4h pir3 f84h porte f64h spbrg2 fe3h plusw1 (1) fc3h adresl fa3h pie3 f83h portd f63h rcreg2 fe2h fsr1h fc2h adcon0 fa2h ipr2 f82h portc f62h txreg2 fe1h fsr1l fc1h adcon1 fa1h pir2 f81h portb f61h txsta2 fe0h bsr fc0h adcon2 fa0h pie2 f80h porta f60h rcsta2 note 1: this is not a physical register. 2: unimplemented registers are read as ? 0 ?. 3: this register is not available on 64-pin devices. ? 2007 microchip technology inc. preliminary ds39774c-page 71 pic18f85j11 family table 5-4: pic18f85j11 family register file summary file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page tosu ? ? ? top-of-stack upper byte (tos<20:16>) ---0 0000 51, 61 tosh top-of-stack high byte (tos<15:8>) 0000 0000 51, 61 tosl top-of-stack low byte (tos<7:0>) 0000 0000 51, 61 stkptr stkful stkunf ? return stack pointer uu-0 0000 51, 62 pclatu ? ?bit 21 (1) holding register for pc<20:16> ---0 0000 51, 61 pclath holding register for pc<15:8> 0000 0000 51, 61 pcl pc low byte (pc<7:0>) 0000 0000 51, 61 tblptru ? ? bit 21 program memory table pointer upper byte (tblptr<20:16>) --00 0000 51, 86 tblptrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 51, 86 tblptrl program memory table pointer low byte (tblptr<7:0>) 0000 0000 51, 86 tablat program memory table latch 0000 0000 51, 86 prodh product register high byte xxxx xxxx 51, 105 prodl product register low byte xxxx xxxx 51, 105 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 51, 109 intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip 1111 1111 51, 110 intcon3 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if 1100 0000 51, 111 indf0 uses contents of fsr0 to address data memory ? value of fsr0 not changed (not a physical register) n/a 51, 77 postinc0 uses contents of fsr0 to address data memory ? value of fsr0 post-incremented (not a physical register) n/a 51, 78 postdec0 uses contents of fsr0 to address data memory ? value of fsr0 post-decremented (not a physical register) n/a 51, 78 preinc0 uses contents of fsr0 to address data memory ? value of fsr0 pre-incremented (not a physical register) n/a 51, 78 plusw0 uses contents of fsr0 to address data memory ? value of fsr0 pre-incremented (not a physical register) ? value of fsr0 offset by w n/a 51, 78 fsr0h ? ? ? ? indirect data memory address pointer 0 high byte ---- xxxx 51, 77 fsr0l indirect data memory address pointer 0 low byte xxxx xxxx 51, 77 wreg working register xxxx xxxx 51 indf1 uses contents of fsr1 to address data memory ? value of fsr1 not changed (not a physical register) n/a 51, 77 postinc1 uses contents of fsr1 to address data memory ? value of fsr1 post-incremented (not a physical register) n/a 51, 78 postdec1 uses contents of fsr1 to address data memory ? value of fsr1 post-decremented (not a physical register) n/a 51, 78 preinc1 uses contents of fsr1 to address data memory ? value of fsr1 pre-incremented (not a physical register) n/a 51, 78 plusw1 uses contents of fsr1 to address data memory ? value of fsr1 pre-incremented (not a physical register) ? value of fsr1 offset by w n/a 51, 78 fsr1h ? ? ? ? indirect data memory address pointer 1 high byte ---- xxxx 52, 77 fsr1l indirect data memory address pointer 1 low byte xxxx xxxx 52, 77 bsr ? ? ? ? bank select register ---- 0000 52, 66 indf2 uses contents of fsr2 to address data memory ? value of fsr2 not changed (not a physical register) n/a 52, 77 postinc2 uses contents of fsr2 to address data memory ? value of fsr2 post-incremented (not a physical register) n/a 52, 78 postdec2 uses contents of fsr2 to address data memory ? value of fsr2 post-decremented (not a physical register) n/a 52, 78 preinc2 uses contents of fsr2 to address data memory ? value of fsr2 pre-incremented (not a physical register) n/a 52, 78 plusw2 uses contents of fsr2 to address data memory ? value of fsr2 pre-incremented (not a physical register) ? value of fsr2 offset by w n/a 52, 78 fsr2h ? ? ? ? indirect data memory address pointer 2 high byte ---- xxxx 52, 77 fsr2l indirect data memory address pointer 2 low byte xxxx xxxx 52, 77 status ? ? ?novzdcc ---x xxxx 52, 75 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify note 1: bit 21 of the pc is only available in test mode and serial programming modes. 2: these registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ? 0 ?. reset states shown are for 80-pin devices. 3: alternate names and definitions for these bits when the mssp module is operating in i 2 c? slave mode. see section 16.4.3.2 ?address masking? for details. 4: the pllen bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ? 0 ?. see section 2.4.3 ?pll frequency multiplier? for details. 5: ra6/ra7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (fosc2 configuration bit = 0 ); otherwise, they are disabled and these bits read as ? 0 ?. pic18f85j11 family ds39774c-page 72 preliminary ? 2007 microchip technology inc. tmr0h timer0 register high byte 0000 0000 52, 149 tmr0l timer0 register low byte xxxx xxxx 52, 149 t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 52, 147 osccon idlen ircf2 ircf1 ircf0 osts iofs scs1 scs0 0100 q000 30, 52 wdtcon regslp ? ? ? ? ? ?swdten 0--- ---0 52, 278 rcon ipen ?cm ri to pd por bor 0-11 11q0 46, 52 tmr1h timer1 register high byte xxxx xxxx 52, 155 tmr1l timer1 register low byte xxxx xxxx 52, 155 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 52, 151 tmr2 timer2 register 0000 0000 52, 158 pr2 timer2 period register 1111 1111 52, 158 t2con ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 -000 0000 52, 157 sspbuf mssp receive buffer/transmit register xxxx xxxx 52, 181, 216 sspadd mssp address register (i 2 c? slave mode). mssp baud rate reload register (i 2 c master mode). 0000 0000 52, 216 sspstat smp cke d/a psr/w ua bf 0000 0000 52, 174, 183 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 52, 175, 184 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 52, 185, 186 gcen ackstat admsk5 (3) admsk4 (3) admsk3 (3) admsk2 (3) admsk1 (3) sen adresh a/d result register high byte xxxx xxxx 53, 259 adresl a/d result register low byte xxxx xxxx 53, 259 adcon0 adcal ? chs3 chs2 chs1 chs0 go/done adon 0-00 0000 53, 251 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 53, 252 adcon2 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 0-00 0000 53, 253 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 0000 0000 53, 267 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 53, 261 tmr3h timer3 register high byte xxxx xxxx 53, 161 tmr3l timer3 register low byte xxxx xxxx 53, 161 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 53, 159 pspcon ibf obf ibov pspmode ? ? ? ? 0000 ---- 53, 159 spbrg1 eusart baud rate generator register 0000 0000 53, 221 rcreg1 eusart receive register 0000 0000 53, 229 txreg1 eusart transmit register 0000 0000 53, 227 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 53, 218 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 0000 000x 53, 219 eecon2 eeprom control register 2 (not a physical register) ---- ---- 53, 84 eecon1 ? ? ? free wrerr wren wr ? ---0 x00- 53, 85 table 5-4: pic18f85j11 family register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify note 1: bit 21 of the pc is only available in test mode and serial programming modes. 2: these registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ? 0 ?. reset states shown are for 80-pin devices. 3: alternate names and definitions for these bits when the mssp module is operating in i 2 c? slave mode. see section 16.4.3.2 ?address masking? for details. 4: the pllen bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ? 0 ?. see section 2.4.3 ?pll frequency multiplier? for details. 5: ra6/ra7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (fosc2 configuration bit = 0 ); otherwise, they are disabled and these bits read as ? 0 ?. ? 2007 microchip technology inc. preliminary ds39774c-page 73 pic18f85j11 family ipr3 ? ? rc2ip tx2ip ? ccp2ip ccp1ip ? --00 -11- 53, 120 pir3 ? ? rc2if tx2if ? ccp2if ccp1if ? --00 -00- 53, 114 pie3 ? ? rc2ie tx2ie ? ccp2ie ccp1ie ? --00 -00- 53, 117 ipr2 oscfip cmip ? ? bclip lvdip tmr3ip ? 11-- 111- 53, 119 pir2 oscfif cmif ? ? bclif lvdif tmr3if ? 00-- 000- 53, 113 pie2 oscfie cmie ? ? bclie lvdie tmr3ie ? 00-- 000- 53, 116 ipr1 pspip adip rc1ip tx1ip sspip ? tmr2ip tmr1ip 1111 1-11 53, 118 pir1 pspif adif rc1if tx1if sspif ?tmr2iftmr1if 0000 0-00 53, 112 pie1 pspie adie rc1ie tx1ie sspie ? tmr2ie tmr1ie 0000 0-00 53, 115 memcon (2) ebdis ?wait1wait0 ? ?wm1wm0 0-00 --00 53, 94 osctune intsrc pllen (4) tun5 tun4 tun3 tun2 tun1 tun0 0000 0000 31, 53 trisj (2) trisj7 trisj6 trisj5 trisj4 trisj3 trisj2 trisj1 trisj0 1111 1111 54, 143 trish (2) trish7 trish6 trish5 trish4 trish3 trish2 trish1 trish0 1111 1111 54, 141 trisg spiod ccp2od ccp1od trisg 4trisg3trisg2t risg1 trisg0 0001 1111 54, 140 trisf trisf7 trisf6 trisf5 t risf4 trisf3 trisf2 trisf1 ? 1111 111- 54, 138 trise trise7 trise6 trise5 trise4 trise3 ? trise1 trise0 1111 1-11 54, 136 trisd trisd7 trisd6 trisd5 trisd 4 trisd3 trisd2 trisd1 trisd0 1111 1111 54, 133 trisc trisc7 trisc6 trisc5 trisc 4 trisc3 trisc2 trisc1 trisc0 1111 1111 54, 130 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 54, 127 trisa trisa7 (5) trisa6 (5) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 1111 1111 54, 125 latj (2) latj7 latj6 latj5 latj4 latj3 latj2 latj1 latj0 xxxx xxxx 54, 143 lath (2) lath7 lath6 lath5 lath4 lath3 lath2 lath1 lath0 xxxx xxxx 54, 141 latg u2od u1od ? latg4 latg3 latg2 latg1 latg0 00-x xxxx 54, 140 latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 ? xxxx xxx- 54, 138 late late7late6late5late4late3late2late1late0 xxxx xxxx 54, 136 latd latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 xxxx xxxx 54, 133 latc latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 xxxx xxxx 54, 130 latb latb7latb6latb5latb4latb3latb2latb1latb0 xxxx xxxx 54, 127 lata lata7 (5) lata6 (5) lata5lata4lata3lata2lata1lata0 xxxx xxxx 54, 125 portj (2) rj7 rj6 rj5 rj4 rj3 rj2 rj1 rj0 xxxx xxxx 54, 143 porth (2) rh7 rh6 rh5 rh4 rh3 rh2 rh1 rh0 xxxx xxxx 54, 141 portg rdpu repu rjpu (2) rg4 rg3 rg2 rg1 rg0 000x xxxx 54, 140 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 ? xxxx xxx- 54, 138 porte re7 re6 re5 re4 re3 ?re1re0 xxxx x-xx 54, 136 portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx 54, 133 portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx 54, 130 portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx 54, 127 porta ra7 (5) ra6 (5) ra5ra4ra3ra2ra1ra0 xx0x 0000 54, 125 table 5-4: pic18f85j11 family register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify note 1: bit 21 of the pc is only available in test mode and serial programming modes. 2: these registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ? 0 ?. reset states shown are for 80-pin devices. 3: alternate names and definitions for these bits when the mssp module is operating in i 2 c? slave mode. see section 16.4.3.2 ?address masking? for details. 4: the pllen bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ? 0 ?. see section 2.4.3 ?pll frequency multiplier? for details. 5: ra6/ra7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (fosc2 configuration bit = 0 ); otherwise, they are disabled and these bits read as ? 0 ?. pic18f85j11 family ds39774c-page 74 preliminary ? 2007 microchip technology inc. spbrgh1 eusart baud rate generator high byte 0000 0000 54, 221 baudcon1 abdovf rcmt ? sckp brg16 ? wue abden 01-0 0-00 54, 220 ccpr1h capture/compare/pwm register 1 high byte xxxx xxxx 54, 164 ccpr1l capture/compare/pwm register 1 low byte xxxx xxxx 54, 164 ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 54, 163 ccpr2h capture/compare/pwm register 2 high byte xxxx xxxx 55, 164 ccpr2l capture/compare/pwm register 2 low byte xxxx xxxx 55, 164 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 55, 163 spbrg2 ausart baud rate generator register 0000 0000 55, 240 rcreg2 ausart receive register 0000 0000 55, 245 txreg2 ausart transmit register 0000 0000 55, 243 txsta2 csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 55, 238 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 0000 000x 55, 239 table 5-4: pic18f85j11 family register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify note 1: bit 21 of the pc is only available in test mode and serial programming modes. 2: these registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ? 0 ?. reset states shown are for 80-pin devices. 3: alternate names and definitions for these bits when the mssp module is operating in i 2 c? slave mode. see section 16.4.3.2 ?address masking? for details. 4: the pllen bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ? 0 ?. see section 2.4.3 ?pll frequency multiplier? for details. 5: ra6/ra7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (fosc2 configuration bit = 0 ); otherwise, they are disabled and these bits read as ? 0 ?. ? 2007 microchip technology inc. preliminary ds39774c-page 75 pic18f85j11 family 5.3.5 status register the status register, shown in register 5-3, contains the arithmetic status of the alu. the status register can be the operand for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc, c, ov or n bits, then the write to these five bits is disabled. these bits are set or cleared according to the device logic. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will set the z bit but leave the other bits unchanged. the status register then reads back as ? 000u u1uu ?. it is recom- mended, therefore, that only bcf , bsf , swapf , movff and movwf instructions are used to alter the status register because these instructions do not affect the z, c, dc, ov or n bits in the status register. for other instructions not affecting any status bits, see the instruction set summaries in table 23-2 and table 23-3. note: the c and dc bits operate as a borrow and digit borrow bit respectively, in subtraction. register 5-3: status register u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ?novzdc (1) c (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4 n: negative bit this bit is used for signed arithmetic (2?s complement). it indicates whether the result was negative (alu msb = 1 ). 1 = result was negative 0 = result was positive bit 3 ov: overflow bit this bit is used for signed arithmetic (2?s complement). it indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit (1) for addwf, addlw, sublw and subwf instructions: 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/borrow bit (2) for addwf, addlw, sublw and subwf instructions: 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow, the polarity is reversed. a subtraction is ex ecuted by adding the 2?s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with eit her bit 4 or bit 3 of the source register. 2: for borrow, the polarity is reversed. a subtraction is executed by adding the 2?s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high or low-order bit of the source register. pic18f85j11 family ds39774c-page 76 preliminary ? 2007 microchip technology inc. 5.4 data addressing modes while the program memory can be addressed in only one way ? through the program counter ? information in the data memory space can be addressed in several ways. for most instructions, the addressing mode is fixed. other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. the addressing modes are: ? inherent ? literal ?direct ?indirect an additional addressing mode, indexed literal offset, is available when the extended instruction set is enabled (xinst configuration bit = 1 ). its operation is discussed in greater detail in section 5.6.1 ?indexed addressing with literal offset? . 5.4.1 inherent and literal addressing many pic18 control instructions do not need any argument at all; they either perform an operation that globally affects the device, or they operate implicitly on one register. this addressing mode is known as inherent addressing. examples include sleep , reset and daw . other instructions work in a similar way, but require an additional explicit argument in the opcode. this is known as literal addressing mode, because they require some literal value as an argument. examples include addlw and movlw , which respectively, add or move a literal value to the w register. other examples include call and goto , which include a 20-bit program memory address. 5.4.2 direct addressing direct addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. the options are specified by the arguments accompanying the instruction. in the core pic18 instruction set, bit-oriented and byte-oriented instructions use some version of direct addressing by default. all of these instructions include some 8-bit literal address as their least significant byte. this address specifies either a register address in one of the banks of data ram ( section 5.3.3 ?general purpose register file? ), or a location in the access bank ( section 5.3.2 ?access bank? ) as the data source for the instruction. the access ram bit ?a? determines how the address is interpreted. when ?a? is ? 1 ?, the contents of the bsr ( section 5.3.1 ?bank select register? ) are used with the address to determine the complete 12-bit address of the register. when ?a? is ? 0 ?, the address is interpreted as being a register in the access bank. addressing that uses the access ram is sometimes also known as direct forced addressing mode. a few instructions, such as movff , include the entire 12-bit address (either source or destination) in their opcodes. in these cases, the bsr is ignored entirely. the destination of the operation?s results is determined by the destination bit ?d?. when ?d? is ? 1 ?, the results are stored back in the source register, overwriting its origi- nal contents. when ?d? is ? 0 ?, the results are stored in the w register. instructions without the ?d? argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the w register. 5.4.3 indirect addressing indirect addressing allows the user to access a location in data memory without giving a fixed address in the instruction. this is done by using file select registers (fsrs) as pointers to the locations to be read or written to. since the fsrs are themselves located in ram as special function registers, they can also be directly manipulated under program control. this makes fsrs very useful in implementing data structures such as tables and arrays in data memory. the registers for indirect addressing are also implemented with indirect file operands (indfs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. this allows for efficient code using loops, such as the example of clearing an entire ram bank in example 5-5. it also enables users to perform indexed addressing and other stack pointer operations for program memory in data memory. example 5-5: how to clear ram (bank 1) using indirect addressing note: the execution of some instructions in the core pic18 instruction set are changed when the pic18 extended instruction set is enabled. see section 5.6 ?data memory and the extended instruction set? for more information. lfsr fsr0, 100h ; next clrf postinc0 ; clear indf ; register then ; inc pointer btfss fsr0h, 1 ; all done with ; bank1? bra next ; no, clear next continue ; yes, continue ? 2007 microchip technology inc. preliminary ds39774c-page 77 pic18f85j11 family 5.4.3.1 fsr registers and the indf operand at the core of indirect addressing are three sets of registers: fsr0, fsr1 and fsr2. each represents a pair of 8-bit registers, fsrnh and fsrnl. the four upper bits of the fsrnh register are not used, so each fsr pair holds a 12-bit value. this represents a value that can address the entire range of the data memory in a linear fashion. the fsr register pairs, then, serve as pointers to data memory locations. indirect addressing is accomplished with a set of indi- rect file operands, indf0 through indf2. these can be thought of as ?virtual? registers: they are mapped in the sfr space but are not physically implemented. reading or writing to a particular indf register actually accesses its corresponding fsr register pair. a read from indf1, for example, reads the data at the address indicated by fsr1h:fsr1l. instructions that use the indf registers as operands actually use the contents of their corresponding fsr as a pointer to the instruc- tion?s target. the indf operand is just a convenient way of using the pointer. because indirect addressing uses a full 12-bit address, data ram banking is not necessary. thus, the current contents of the bsr and the access ram bit have no effect on determining the target address. figure 5-10: indirect addressing fsr1h:fsr1l 0 7 data memory 000h 100h 200h 300h f00h e00h fffh bank 0 bank 1 bank 2 bank 14 bank 15 bank 3 through bank 13 addwf, indf1, 1 0 7 using an instruction with one of the indirect addressing registers as the operand.... ...uses the 12-bit address stored in the fsr pair associated with that register.... ...to determine the data memory location to be used in that operation. in this case, the fsr1 pair contains fcch. this means the contents of location fcch will be added to that of the w register and stored back in fcch. xxxx 1111 11001100 pic18f85j11 family ds39774c-page 78 preliminary ? 2007 microchip technology inc. 5.4.3.2 fsr registers and postinc, postdec, preinc and plusw in addition to the indf operand, each fsr register pair also has four additional indirect operands. like indf, these are ?virtual? registers that cannot be indirectly read or written to. accessing these registers actually accesses the associated fsr register pair, but also performs a specific action on its stored value. they are: ? postdec: accesses the fsr value, then automatically decrements it by ? 1 ? afterwards ? postinc: accesses the fsr value, then automatically increments it by ? 1 ? afterwards ? preinc: increments the fsr value by ? 1 ?, then uses it in the operation ? plusw: adds the signed value of the w register (range of -127 to 128) to that of the fsr and uses the new value in the operation in this context, accessing an indf register uses the value in the fsr registers without changing them. similarly, accessing a plusw register gives the fsr value offset by the value in the w register; neither value is actually changed in the operation. accessing the other virtual registers changes the value of the fsr registers. operations on the fsrs with postdec, postinc and preinc affect the entire register pair; that is, roll- overs of the fsrnl register from ffh to 00h carry over to the fsrnh register. on the other hand, results of these operations do not change the value of any flags in the status register (e.g., z, n, ov, etc.). the plusw register can be used to implement a form of indexed addressing in the data memory space. by manipulating the value in the w register, users can reach addresses that are fixed offsets from pointer addresses. in some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 5.4.3.3 operations by fsrs on fsrs indirect addressing operations that target other fsrs or virtual registers represent special cases. for exam- ple, using an fsr to point to one of the virtual registers will not result in successful operations. as a specific case, assume that fsr0h:fsr0l contain fe7h, the address of indf1. attempts to read the value of the indf1, using indf0 as an operand, will return 00h. attempts to write to indf1, using indf0 as the operand, will result in a nop . on the other hand, using the virtual registers to write to an fsr pair may not occur as planned. in these cases, the value will be written to the fsr pair but without any incrementing or decrementing. thus, writing to indf2 or postdec2 will write the same value to the fsr2h:fsr2l. since the fsrs are physical registers mapped in the sfr space, they can be manipulated through all direct operations. users should proceed cautiously when working on these registers, particularly if their code uses indirect addressing. similarly, operations by indirect addressing are gener- ally permitted on all other sfrs. users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 5.5 program memory and the extended instruction set the operation of program memory is unaffected by the use of the extended instruction set. enabling the extended instruction set adds five additional two-word commands to the existing pic18 instruction set: addfsr , callw , movsf , movss and subfsr . these instructions are executed as described in section 5.2.4 ?two-word instructions? . ? 2007 microchip technology inc. preliminary ds39774c-page 79 pic18f85j11 family 5.6 data memory and the extended instruction set enabling the pic18 extended instruction set (xinst configuration bit = 1 ) significantly changes certain aspects of data memory and its addressing. specifically, the use of the access bank for many of the core pic18 instructions is different; this is due to the introduction of a new addressing mode for the data memory space. this mode also alters the behavior of indirect addressing using fsr2 and its associated operands. what does not change is just as important. the size of the data memory space is unchanged, as well as its linear addressing. the sfr map remains the same. core pic18 instructions can still operate in both direct and indirect addressing mode; inherent and literal instructions do not change at all. indirect addressing with fsr0 and fsr1 also remains unchanged. 5.6.1 indexed addressing with literal offset enabling the pic18 extended instruction set changes the behavior of indirect addressing using the fsr2 register pair and its associated file operands. under the proper conditions, instructions that use the access bank ? that is, most bit-oriented and byte-oriented instructions ? can invoke a form of indexed addressing using an offset specified in the instruction. this special addressing mode is known as indexed addressing with literal offset, or indexed literal offset mode. when using the extended instruction set, this addressing mode requires the following: ? the use of the access bank is forced (?a? = 0 ); and ? the file address argument is less than or equal to 5fh. under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the bsr in direct addressing) or as an 8-bit address in the access bank. instead, the value is interpreted as an offset value to an address pointer specified by fsr2. the offset and the contents of fsr2 are added to obtain the target address of the operation. 5.6.2 instructions affected by indexed literal offset mode any of the core pic18 instructions that can use direct addressing are potentially affected by the indexed literal offset addressing mode. this includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard pic18 instruction set. instruc- tions that only use inherent or literal addressing modes are unaffected. additionally, byte-oriented and bit-oriented instructions are not affected if they use the access bank (access ram bit is ? 1 ?) or include a file address of 60h or above. instructions meeting these criteria will continue to execute as before. a comparison of the different possible addressing modes when the extended instruction set is enabled is shown in figure 5-11. those who desire to use byte-oriented or bit-oriented instructions in the indexed literal offset mode should note the changes to assembler syntax for this mode. this is described in more detail in section 23.2.1 ?extended instruction syntax? . pic18f85j11 family ds39774c-page 80 preliminary ? 2007 microchip technology inc. figure 5-11: comparing addressing options for bit-oriented and byte-oriented instructions (extended instruction set enabled) example instruction: addwf, f, d, a (opcode: 0010 01da ffff ffff ) when a = 0 and f 60h: the instruction executes in direct forced mode. ?f? is interpreted as a location in the access ram between 060h and fffh. this is the same as locations f60h to fffh (bank 15) of data memory. locations below 060h are not available in this addressing mode. when a = 0 and f 5fh: the instruction executes in indexed literal offset mode. ?f? is interpreted as an offset to the address value in fsr2. the two are added together to obtain the address of the target register for the instruction. the address can be anywhere in the data memory space. note that in this mode, the correct syntax is now: addwf [k], d where ?k? is the same as ?f?. when a = 1 (all values of f): the instruction executes in direct mode (also known as direct long mode). ?f? is interpreted as a location in one of the 16 banks of the data memory space. the bank is designated by the bank select register (bsr). the address can be in any implemented bank in the data memory space. 000h 060h 100h f00h f40h fffh valid range 00h 60h ffh data memory access ram bank 0 bank 1 through bank 14 bank 15 sfrs 000h 060h 100h f00h f40h fffh data memory bank 0 bank 1 through bank 14 bank 15 sfrs fsr2h fsr2l ffffffff 001001da ffffffff 001001da 000h 060h 100h f00h f40h fffh data memory bank 0 bank 1 through bank 14 bank 15 sfrs for ?f? bsr 00000000 ? 2007 microchip technology inc. preliminary ds39774c-page 81 pic18f85j11 family 5.6.3 mapping the access bank in indexed literal offset mode the use of indexed literal offset addressing mode effectively changes how the lower part of access ram (00h to 5fh) is mapped. rather than containing just the contents of the bottom part of bank 0, this mode maps the contents from bank 0 and a user-defined ?window? that can be located anywhere in the data memory space. the value of fsr2 establishes the lower bound- ary of the addresses mapped into the window, while the upper boundary is defined by fsr2 plus 95 (5fh). addresses in the access ram above 5fh are mapped as previously described (see section 5.3.2 ?access bank? ). an example of access bank remapping in this addressing mode is shown in figure 5-12. remapping of the access bank applies only to opera- tions using the indexed literal offset mode. operations that use the bsr (access ram bit is ? 1 ?) will continue to use direct addressing as before. any indirect or indexed addressing operation that explicitly uses any of the indirect file operands (including fsr2) will con- tinue to operate as standard indirect addressing. any instruction that uses the access bank, but includes a register address of greater than 05fh, will use direct addressing and the normal access bank map. 5.6.4 bsr in indexed literal offset mode although the access bank is remapped when the extended instruction set is enabled, the operation of the bsr remains unchanged. direct addressing, using the bsr to select the data memory bank, operates in the same manner as previously described. figure 5-12: remapping the access bank with indexed literal offset addressing data memory 000h 100h 200h f60h f00h fffh bank 1 bank 15 bank 2 through bank 14 sfrs 05fh addwf f, d, a fsr2h:fsr2l = 120h locations in the region from the fsr2 pointer (120h) to the pointer plus 05fh (17fh) are mapped to the bottom of the access ram (000h-05fh). special function registers at f60h through fffh are mapped to 60h through ffh, as usual. bank 0 addresses below 5fh are not available in this mode. they can still be addressed by using the bsr. access bank 00h ffh bank 0 sfrs bank 1 ?window? not accessible window example situation: 120h 17fh 5fh 60h pic18f85j11 family ds39774c-page 82 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. preliminary ds39774c-page 83 pic18f85j11 family 6.0 flash program memory the flash program memory is readable, writable and erasable during normal operation over the entire v dd range. a read from program memory is executed on one byte at a time. a write to program memory is executed on blocks of 64 bytes at a time. program memory is erased in blocks of 1024 bytes at a time. a bulk erase operation may not be issued from user code. writing or erasing program memory will cease instruction fetches until the operation is complete. the program memory cannot be accessed during the write or erase, therefore, code cannot execute. an internal programming timer terminates program memory writes and erases. a value written to program memory does not need to be a valid instruction. executing a program memory location that forms an invalid instruction results in a nop . 6.1 table reads and table writes in order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data ram: ? table read ( tblrd ) ? table write ( tblwt ) the program memory space is 16 bits wide, while the data ram space is 8 bits wide. table reads and table writes move data between these two memory spaces through an 8-bit register (tablat). table read operations retrieve data from program memory and place it into the data ram space. figure 6-1 shows the operation of a table read with program memory and data ram. table write operations store data from the data memory space into holding registers in program memory. the procedure to write the contents of the holding registers into program memory is detailed in section 6.5 ?writing to flash program memory? . figure 6-2 shows the operation of a table write with program memory and data ram. table operations work with byte entities. a table block containing data, rather than program instructions, is not required to be word-aligned. therefore, a table block can start and end at any byte address. if a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. figure 6-1: table read operation ta b l e p o i n t e r (1) table latch (8-bit) program memory tblptrh tblptrl tablat tblptru instruction: tblrd * note 1: table pointer register points to a byte in program memory. program memory (tblptr) pic18f85j11 family ds39774c-page 84 preliminary ? 2007 microchip technology inc. figure 6-2: table write operation 6.2 control registers several control registers are used in conjunction with the tblrd and tblwt instructions. these include the: ? eecon1 register ? eecon2 register ? tablat register ? tblptr registers 6.2.1 eecon1 and eecon2 registers the eecon1 register (register 6-1) is the control register for memory accesses. the eecon2 register is not a physical register; it is used exclusively in the memory write and erase sequences. reading eecon2 will read all ? 0 ?s. the free bit, when set, will allow a program memory erase operation. when free is set, the erase operation is initiated on the next wr command. when free is clear, only writes are enabled. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set in hardware when the wr bit is set and cleared when the internal programming timer expires and the write operation is complete. the wr control bit initiates write operations. the bit cannot be cleared, only set, in software. it is cleared in hardware at the completion of the write operation. table pointer (1) table latch (8-bit) tblptrh tblptrl tablat program memory (tblptr) tblptru instruction: tblwt * note 1: table pointer actually points to one of 64 holding registers, the address of which is determined by tblptrl<5:0>. the process for physically writing dat a to the program memory array is discussed in section 6.5 ?writing to flash program memory? . holding registers program memory note: during normal operation, the wrerr is read as ? 1 ?. this can indicate that a write operation was prematurely terminated by a reset, or a write operation was attempted improperly. ? 2007 microchip technology inc. preliminary ds39774c-page 85 pic18f85j11 family register 6-1: eecon1: eeprom control register 1 u-0 u-0 u-0 r/w-0 r/w-x r/w-0 r/s-0 u-0 ? ? ? free wrerr wren wr ? bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit s = set only bit (cannot be cleared in software) -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4 free: flash row erase enable bit 1 = erase the program memory row addressed by tblptr on the next wr command (cleared by completion of erase operation) 0 = perform write only bit 3 wrerr: flash program error flag bit 1 = a write operation is prematurely terminated (a ny reset during self-timed programming in normal operation, or an improper write attempt) 0 = the write operation completed bit 2 wren: flash program write enable bit 1 = allows write cycles to flash program memory 0 = inhibits write cycles to flash program memory bit 1 wr: write control bit 1 = initiates a program memory erase cycle or write cycle (the operation is self-timed and the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle is complete bit 0 unimplemented: read as ? 0 ? pic18f85j11 family ds39774c-page 86 preliminary ? 2007 microchip technology inc. 6.2.2 table latch register (tablat) the table latch (tablat) is an 8-bit register mapped into the sfr space. the table latch register is used to hold 8-bit data during data transfers between program memory and data ram. 6.2.3 table pointer register (tblptr) the table pointer (tblptr) register addresses a byte within the program memory. the tblptr is comprised of three sfr registers: table pointer upper byte, table pointer high byte and table pointer low byte (tblptru:tblptrh:tblptrl). these three regis- ters join to form a 22-bit wide pointer. the low-order 21 bits allow the device to address up to 2 mbytes of program memory space. the 22nd bit allows access to the device id, the user id and the configuration bits. the table pointer register, tblptr, is used by the tblrd and tblwt instructions. these instructions can update the tblptr in one of four ways based on the table operation. these operations are shown in table 6-1. these operations on the tblptr only affect the low-order 21 bits. 6.2.4 table pointer boundaries tblptr is used in reads, writes and erases of the flash program memory. when a tblrd is executed, all 22 bits of the tblptr determine which byte is read from program memory into tablat. when a tblwt is executed, the seven lsbs of the table pointer register (tblptr<6:0>) determine which of the 64 program memory holding registers is written to. when the timed write to program memory begins (via the wr bit), the 12 msbs of the tblptr (tblptr<21:10>) determine which program memory block of 1024 bytes is written to. for more detail, see section 6.5 ?writing to flash program memory? . when an erase of program memory is executed, the 12 msbs of the table pointer register point to the 1024-byte block that will be erased. the least significant bits are ignored. figure 6-3 describes the relevant boundaries of the tblptr based on flash program memory operations. table 6-1: table pointer operations with tblrd and tblwt instructions figure 6-3: table pointer boundaries based on operation example operation on table pointer tblrd* tblwt* tblptr is not modified tblrd*+ tblwt*+ tblptr is incremented after the read/write tblrd*- tblwt*- tblptr is decremented after the read/write tblrd+* tblwt+* tblptr is incremented before the read/write 21 16 15 87 0 erase: tblptr<21:10> table write: tblptr<21:6> table read: tblptr<21:0> tblptrl tblptrh tblptru ? 2007 microchip technology inc. preliminary ds39774c-page 87 pic18f85j11 family 6.3 reading the flash program memory the tblrd instruction is used to retrieve data from program memory and places it into data ram. table reads from program memory are performed one byte at a time. tblptr points to a byte address in program space. executing tblrd places the byte pointed to into tablat. in addition, tblptr can be modified automatically for the next table read operation. the internal program memory is typically organized by words. the least significant bit of the address selects between the high and low bytes of the word. figure 6-4 shows the interface between the internal program memory and the tablat. figure 6-4: reads from flash program memory example 6-1: reading a flash program memory word (even byte address) program memory (odd byte address) tblrd tablat tblptr = xxxxx1 fetch instruction register (ir) read register tblptr = xxxxx0 movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the word movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl read_word tblrd*+ ; read into tablat and increment movf tablat, w ; get data movwf word_even tblrd*+ ; read into tablat and increment movf tablat, w ; get data movf word_odd pic18f85j11 family ds39774c-page 88 preliminary ? 2007 microchip technology inc. 6.4 erasing flash program memory the minimum erase block is 512 words or 1024 bytes. only through the use of an external programmer, or through icsp control, can larger blocks of program memory be bulk erased. word erase in the flash array is not supported. when initiating an erase sequence from the micro- controller itself, a block of 1024 bytes of program memory is erased. the most significant 12 bits of the tblptr<21:10> point to the block being erased; tblptr<9:0> are ignored. the eecon1 register commands the erase operation. the wren bit must be set to enable write operations. the free bit is set to select an erase operation. for protection, the write initiate sequence for eecon2 must be used. a long write is necessary for erasing the internal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. 6.4.1 flash program memory erase sequence the sequence of events for erasing a block of internal program memory location is: 1. load table pointer register with address of row being erased. 2. set the wren and free bits (eecon1<2,4>) to enable the erase operation. 3. disable interrupts. 4. write 55h to eecon2. 5. write 0aah to eecon2. 6. set the wr bit. this will begin the row erase cycle. 7. the cpu will stall for duration of the erase for t iw (see parameter d133a). 8. re-enable interrupts. example 6-2: erasing a flash program memory row movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl erase_row bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable row erase operation bcf intcon, gie ; disable interrupts required movlw 55h sequence movwf eecon2 ; write 55h movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start erase (cpu stall) bsf intcon, gie ; re-enable interrupts ? 2007 microchip technology inc. preliminary ds39774c-page 89 pic18f85j11 family 6.5 writing to flash program memory the minimum programming block is 32 words or 64 bytes. word or byte programming is not supported. table writes are used internally to load the holding registers needed to program the flash memory. there are 64 holding registers used by the table writes for programming. since the table latch (tablat) is only a single byte, the tblwt instruction may need to be executed 64 times for each programming operation. all of the table write oper- ations will essentially be short writes because only the holding registers are written. at the end of updating the 64 holding registers, the eecon1 register must be written to in order to start the programming operation with a long write. the long write is necessary for programming the inter- nal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. the on-chip timer controls the write time. the write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. figure 6-5: table writes to flash program memory 6.5.1 flash program memory write sequence the sequence of events for programming an internal program memory location should be: 1. read 1024 bytes into ram. 2. update data values in ram as necessary. 3. load table pointer register with address being erased. 4. execute the row erase procedure. 5. load table pointer register with address of first byte being written, minus 1. 6. write the 64 bytes into the holding registers with auto-increment. 7. set the wren bit (eecon1<2>) to enable byte writes. 8. disable interrupts. 9. write 55h to eecon2. 10. write 0aah to eecon2. 11. set the wr bit. this will begin the write cycle. 12. the cpu will stall for duration of the write for t iw (see parameter d133a). 13. re-enable interrupts. 14. repeat steps 6 through 13 until all 1024 bytes are written to program memory. 15. verify the memory (table read). an example of the required code is shown in example 6-3 on the following page. note 1: unlike previous pic ? mcus, members of the pic18f85j11 family do not reset the holding registers after a write occurs. the holding registers must be cleared or over- written before a programming sequence. 2: to maintain the endurance of the program memory cells, each flash byte should not be programmed more than one time between erase operations. before attempting to modify the contents of the target cell a second time, a row erase of the target row, or a bulk erase of the entire memory, must be performed. tablat tblptr = xxxx3f tblptr = xxxxx1 tblptr = xxxxx0 write register tblptr = xxxxx2 program memory holding register holding register holding register holding register 8 8 8 8 note: before setting the wr bit, the table pointer address needs to be within the intended address range of the 64 bytes in the holding register. pic18f85j11 family ds39774c-page 90 preliminary ? 2007 microchip technology inc. example 6-3: writing to flash program memory movlw code_addr_upper ; load tblptr with the base address movwf tblptru ; of the memory block, minus 1 movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl erase_block bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable row erase operation bcf intcon, gie ; disable interrupts movlw 55h movwf eecon2 ; write 55h movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start erase (cpu stall) bsf intcon, gie ; re-enable interrupts movlw d'16' movwf write_counter ; need to write 16 blocks of 64 to write ; one erase block of 1024 restart_buffer movlw d'64' movwf counter movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low movwf fsr0l fill_buffer ... ; read the new data from i2c, spi, ; psp, usart, etc. write_buffer movlw d?64 ; number of bytes in holding register movwf counter write_byte_to_hregs movff postinc0, wreg ; get low byte of buffer data movwf tablat ; present data to table latch tblwt+* ; write data, perform a short write ; to internal tblwt holding register. decfsz counter ; loop until buffers are full bra write_byte_to_hregs program_memory bsf eecon1, wren ; enable write to memory bcf intcon, gie ; disable interrupts movlw 55h required movwf eecon2 ; write 55h sequence movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start program (cpu stall) bsf intcon, gie ; re-enable interrupts bcf eecon1, wren ; disable write to memory decfsz write_counter ; done with one write cycle bra restart_buffer ; if not done replacing the erase block ? 2007 microchip technology inc. preliminary ds39774c-page 91 pic18f85j11 family 6.5.2 write verify depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. 6.5.3 unexpected termination of write operation if a write is terminated by an unplanned event, such as loss of power or an unexpected reset, the memory location just programmed should be verified and repro- grammed if needed. if the write operation is interrupted by a mclr reset or a wdt time-out reset during normal operation, the user can check the wrerr bit and rewrite the location(s) as needed. 6.6 flash program operation during code protection see section 22.6 ?program verification and code protection? for details on code protection of flash program memory. table 6-2: registers associated with program flash memory name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page tblptru ? ? bit 21 program memory table pointer upper byte (tblptr<20:16>) 51 tbpltrh program memory table pointer high byte (tblptr<15:8>) 51 tblptrl program memory table pointer low byte (tblptr<7:0>) 51 tablat program memory table latch 51 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 eecon2 eeprom control register 2 (not a physical register) 53 eecon1 ? ? ? free wrerr wren wr ?53 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used during program memory access. pic18f85j11 family ds39774c-page 92 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. preliminary ds39774c-page 93 pic18f85j11 family 7.0 external memory bus the external memory bus allows the device to access external memory devices (such as flash, eprom, sram, etc.) as program or data memory. it supports both 8 and 16-bit data width modes and three address widths of up to 20 bits. the bus is implemented with 28 pins, multiplexed across four i/o ports. three ports (portd, porte and porth) are multiplexed with the address/data bus for a total of 20 available lines, while portj is multiplexed with the bus control signals. a list of the pins and their functions is provided in table 7-1. table 7-1: pic18f85j11 family external bus ? i/o port functions note: the external memory bus is not implemented on 64-pin devices. name port bit external memory bus function rd0/ad0 portd 0 address bit 0 or data bit 0 rd1/ad1 portd 1 address bit 1 or data bit 1 rd2/ad2 portd 2 address bit 2 or data bit 2 rd3/ad3 portd 3 address bit 3 or data bit 3 rd4/ad4 portd 4 address bit 4 or data bit 4 rd5/ad5 portd 5 address bit 5 or data bit 5 rd6/ad6 portd 6 address bit 6 or data bit 6 rd7/ad7 portd 7 address bit 7 or data bit 7 re0/ad8 porte 0 address bit 8 or data bit 8 re1/ad9 porte 1 address bit 9 or data bit 9 re2/ad10 porte 2 address bit 10 or data bit 10 re3/ad11 porte 3 address bit 11 or data bit 11 re4/ad12 porte 4 address bit 12 or data bit 12 re5/ad13 porte 5 address bit 13 or data bit 13 re6/ad14 porte 6 address bit 14 or data bit 14 re7/ad15 porte 7 address bit 15 or data bit 15 rh0/a16 porth 0 address bit 16 rh1/a17 porth 1 address bit 17 rh2/a18 porth 2 address bit 18 rh3/a19 porth 3 address bit 19 rj0/ale portj 0 address latch enable (ale) control pin rj1/oe portj 1 output enable (oe ) control pin rj2/wrl portj 2 write low (wrl ) control pin rj3/wrh portj 3 write high (wrh ) control pin rj4/ba0 portj 4 byte address bit 0 (ba0) rj5/ce portj 5 chip enable (ce ) control pin rj6/lb portj 6 lower byte enable (lb ) control pin rj7/ub portj 7 upper byte enable (ub ) control pin note: for the sake of clarity, only i/o port and external bus assignments are shown here. one or more additional multiplexed features may be available on some pins. pic18f85j11 family ds39774c-page 94 preliminary ? 2007 microchip technology inc. 7.1 external memory bus control the operation of the interface is controlled by the memcon register (register 7-1). this register is available in all program memory modes except micro- controller mode. in this mode, the register is disabled and cannot be written to. the ebdis bit (memcon<7>) controls the operation of the bus and related port functions. clearing ebdis enables the interface and disables the i/o functions of the ports, as well as any other functions multiplexed to those pins. setting the bit enables the i/o ports and other functions, but allows the interface to override everything else on the pins when an external memory operation is required. by default, the external bus is always enabled and disables all other i/o. the operation of the ebdis bit is also influenced by the program memory mode being used. this is discussed in more detail in section 7.5 ?program memory modes and the external memory bus? . the wait bits allow for the addition of wait states to external memory operations. the use of these bits is discussed in section 7.3 ?wait states? . the wm bits select the particular operating mode used when the bus is operating in 16-bit data width mode. these are discussed in more detail in section 7.6 ?16-bit data width modes? . these bits have no effect when an 8-bit data width mode is selected. register 7-1: memcon: external memory bus control register r/w-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 ebdis ?wait1wait0 ? ?wm1wm0 bit 15 bit 8 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ebdis : external bus disable bit 1 = external bus enabled when microcontroller accesses external memory; otherwise, all external bus drivers are mapped as i/o ports 0 = external bus always enabled, i/o ports are disabled bit 6 unimplemented : read as ? 0 ? bit 5-4 wait1:wait0: table reads and writes bus cycle wait count bits 11 = table reads and writes will wait 0 t cy 10 = table reads and writes will wait 1 t cy 01 = table reads and writes will wait 2 t cy 00 = table reads and writes will wait 3 t cy bit 3-2 unimplemented : read as ? 0 ? bit 1-0 wm1:wm0: tblwt operation with 16-bit data bus width select bits 1x = word write mode: tablat0 and tablat1 word output, wrh active when tablat1 written 01 = byte select mode: tablat data copied on both msb and lsb, wrh and (ub or lb ) will activate 00 = byte write mode: tablat data copied on both msb and lsb, wrh or wrl will activate ? 2007 microchip technology inc. preliminary ds39774c-page 95 pic18f85j11 family 7.2 address and data width the pic18f85j11 family of devices can be indepen- dently configured for different address and data widths on the same memory bus. both address and data width are set by configuration bits in the config3l register. as configuration bits, this means that these options can only be configured by programming the device and are not controllable in software. the bw bit selects an 8-bit or 16-bit data bus width. setting this bit (default) selects a data width of 16 bits. the emb1:emb0 bits determine both the program memory mode and the address bus width. the avail- able options are 20-bit, 16-bit and 12-bit, as well as the default microcontroller mode (external bus disabled). selecting a 16-bit or 12-bit width makes a correspond- ing number of high-order lines available for i/o func- tions; these pins are no longer affected by the setting of the ebdis bit. for example, selecting a 16-bit address mode (emb1:emb0 = 01 ) disables a19:a16 and allows porth<3:0> to function without interruptions from the bus. using the smaller address widths allows users to tailor the memory bus to the size of the exter- nal memory space for a particular design while freeing up pins for dedicated i/o operation. because the emb bits have the effect of disabling pins for memory bus operations, it is important to always select an address width at least equal to the data width. if a 12-bit address width is used with a 16-bit data width, the upper four bits of data will not be available on the bus. all combinations of address and data widths require multiplexing of address and data information on the same lines. the address and data multiplexing, as well as i/o ports made available by the use of smaller address widths, are summarized in table 7-2. 7.2.1 address shifting on the external bus by default, the address presented on the external bus is the value of the pc. in practical terms, this means that addresses in the external memory device below the top of on-chip memory are unavailable to the micro- controller. to access these physical locations, the glue logic between the microcontroller and the external memory must somehow translate addresses. to simplify the interface, the external bus offers an extension of extended microcontroller mode that automatically performs address shifting. this feature is controlled by the eashft configuration bit. setting this bit offsets addresses on the bus by the size of the microcontroller?s on-chip program memory and sets the bottom address at 0000h. this allows the device to use the entire range of physical addresses of the external memory. 7.2.2 21-bit addressing as an extension of 20-bit address width operation, the external memory bus can also fully address a 2-mbyte memory space. this is done by using the bus address bit 0 (ba0) control line as the least significant bit of the address. the ub and lb control signals may also be used with certain memory devices to select the upper and lower bytes within a 16-bit wide data word. this addressing mode is available in both 8-bit and certain 16-bit data width modes. additional details are provided in section 7.6.3 ?16-bit byte select mode? and section 7.7 ?8-bit data width mode? . table 7-2: address and data lines for different address and data widths data width address width multiplexed data and address lines (and corresponding ports) address-only lines (and corresponding ports) ports available for i/o 8-bit 12-bit ad7:ad0 (portd<7:0>) ad11:ad8 (porte<3:0>) porte<7:4>, all of porth 16-bit ad15:ad8 (porte<7:0>) all of porth 20-bit a19:a16, ad15:ad8 (porth<3:0>, porte<7:0>) ? 16-bit 16-bit ad15:ad0 (portd<7:0>, porte<7:0>) ? all of porth 20-bit a19:a16 (porth<3:0>) ? pic18f85j11 family ds39774c-page 96 preliminary ? 2007 microchip technology inc. 7.3 wait states while it may be assumed that external memory devices will operate at the microcontroller clock rate, this is often not the case. in fact, many devices require longer times to write or retrieve data than the time allowed by the execution of table read or table write operations. to compensate for this, the external memory bus can be configured to add a fixed delay to each table opera- tion using the bus. wait states are enabled by setting the wait configuration bit. when enabled, the amount of delay is set by the wait1:wait0 bits (memcon<5:4>). the delay is based on multiples of microcontroller instruction cycle time and are added following the instruction cycle when the table operation is executed. the range is from no delay to 3 t cy (default value). 7.4 port pin weak pull-ups with the exception of the upper address lines, a19:a16, the pins associated with the external memory bus are equipped with weak pull-ups. the pull-ups are controlled by the upper three bits of the portg register. they are named rdpu, repu and rjpu and control pull-ups on portd, porte and portj, respectively. setting one of these bits enables the corresponding pull-ups for that port. all pull-ups are disabled by default on all device resets. 7.5 program memory modes and the external memory bus the pic18f85j11 family of devices are capable of operating in one of two program memory modes, using combinations of on-chip and external program memory. the functions of the multiplexed port pins depend on the program memory mode selected, as well as the setting of the ebdis bit. in microcontroller mode, the bus is not active and the pins have their port functions only. writes to the memcom register are not permitted. the reset value of ebdis (? 0 ?) is ignored and emb pins behave as i/o ports. in extended microcontroller mode, the external program memory bus shares i/o port functions on the pins. when the device is fetching or doing table read/table write operations on the external program memory space, the pins will have the external bus function. if the device is fetching and accessing internal program memory locations only, the ebdis control bit will change the pins from external memory to i/o port functions. when ebdis = 0 , the pins function as the external bus. when ebdis = 1 , the pins function as i/o ports. if the device fetches or accesses external memory while ebdis = 1 , the pins will switch to the external bus. if the ebdis bit is set by a program executing from external memory, the action of setting the bit will be delayed until the program branches into the internal memory. at that time, the pins will change from external bus to i/o ports. if the device is executing out of internal memory when ebdis = 0 , the memory bus address/data and control pins will not be active. they will go to a state where the active address/data pins are tri-state; the ce , oe , wrh , wrl , ub and lb signals are ? 1 ? and ale and ba0 are ? 0 ?. note that only those pins associated with the current address width are forced to tri-state; the other pins continue to function as i/o. in the case of 16-bit address width, for example, only ad<15:0> (portd and porte) are affected; a19:a16 (porth<3:0>) continue to function as i/o. in all external memory modes, the bus takes priority over any other peripherals that may share pins with it. this includes the parallel slave port and serial commu- nication modules which would otherwise take priority over the i/o port. 7.6 16-bit data width modes in 16-bit data width mode, the external memory interface can be connected to external memories in three different configurations: ? 16-bit byte write ? 16-bit word write ? 16-bit byte select the configuration to be used is determined by the wm1:wm0 bits in the memcon register (memcon<1:0>). these three different configurations allow the designer maximum flexibility in using both 8-bit and 16-bit devices with 16-bit data. for all 16-bit data width modes, the address latch enable (ale) pin indicates that the address bits, ad<15:0>, are available on the external memory inter- face bus. following the address latch, the output enable signal (oe ) will enable both bytes of program memory at once to form a 16-bit instruction word. the chip enable signal (ce ) is active at any time that the microcontroller accesses external memory, whether reading or writing. it is inactive (asserted high) whenever the device is in sleep mode. in byte select mode, jedec standard flash memories will require ba0 for the byte address line and one i/o line to select between byte and word mode. the other 16-bit data width modes do not need ba0. jedec standard static ram memories will use the ub or lb signals for byte selection. ? 2007 microchip technology inc. preliminary ds39774c-page 97 pic18f85j11 family 7.6.1 16-bit byte write mode figure 7-1 shows an example of 16-bit byte write mode for pic18f85j11 family devices. this mode is used for two separate 8-bit memories connected for 16-bit operation. this generally includes basic eprom and flash devices. it allows table writes to byte-wide external memories. during a tblwt instruction cycle, the tablat data is presented on the upper and lower bytes of the ad15:ad0 bus. the appropriate wrh or wrl control line is strobed on the lsb of the tblptr. figure 7-1: 16-bit byte write mode example ad<7:0> a<19:16> (1) ale d<15:8> 373 a pic18f85j11 family ds39774c-page 98 preliminary ? 2007 microchip technology inc. 7.6.2 16-bit word write mode figure 7-2 shows an example of 16-bit word write mode for pic18f85j11 family devices. this mode is used for word-wide memories which include some of the eprom and flash-type memories. this mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories. this method makes a distinction between tblwt cycles to even or odd addresses. during a tblwt cycle to an even address (tblptr<0> = 0 ), the tablat data is transferred to a holding latch and the external address data bus is tri-stated for the data portion of the bus cycle. no write signals are activated. during a tblwt cycle to an odd address (tblptr<0> = 1 ), the tablat data is presented on the upper byte of the ad15:ad0 bus. the contents of the holding latch are presented on the lower byte of the ad15:ad0 bus. the wrh signal is strobed for each write cycle; the wrl pin is unused. the signal on the ba0 pin indicates the lsb of the tblptr, but it is left unconnected. instead, the ub and lb signals are active to select both bytes. the obvious limitation to this method is that the table write must be done in pairs on a specific word boundary to correctly write a word location. figure 7-2: 16-bit word write mode example ad<7:0> pic18f85j11 ad<15:8> ale 373 a<20:1> 373 oe wrh a<19:16> (1) a ? 2007 microchip technology inc. preliminary ds39774c-page 99 pic18f85j11 family 7.6.3 16-bit byte select mode figure 7-3 shows an example of 16-bit byte select mode. this mode allows table write operations to word-wide external memories with byte selection capability. this generally includes both word-wide flash and sram devices. during a tblwt cycle, the tablat data is presented on the upper and lower byte of the ad15:ad0 bus. the wrh signal is strobed for each write cycle; the wrl pin is not used. the ba0 or ub /lb signals are used to select the byte to be written, based on the least significant bit of the tblptr register. flash and sram devices use different control signal combinations to implement byte select mode. jedec standard flash memories require that a controller i/o port pin be connected to the memory?s byte/word pin to provide the select signal. they also use the ba0 signal from the controller as a byte address. jedec standard static ram memories, on the other hand, use the ub or lb signals to select the byte. figure 7-3: 16-bit byte select mode example ad<7:0> pic18f85j11 ad<15:8> ale 373 a<20:1> 373 oe wrh a<19:16> (2) wrl ba0 jedec word a pic18f85j11 family ds39774c-page 100 preliminary ? 2007 microchip technology inc. 7.6.4 16-bit mode timing the presentation of control signals on the external memory bus is different for the various operating modes. typical signal timing diagrams are shown in figure 7-4 and figure 7-5. figure 7-4: external me mory bus timing for tblrd (extended microcontroller mode) figure 7-5: external memory bus timing for sleep (extended microcontroller mode) q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe ad<15:0> ce opcode fetch opcode fetch opcode fetch tblrd * tblrd cycle 1 addlw 55h from 000100h q2 q1 q3 q4 0ch cf33h tblrd 92h from 199e67h 9256h from 000104h memory cycle instruction execution inst(pc ? 2) tblrd cycle 2 movlw 55h from 000102h movlw q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe 3aaah ad<15:0> 00h 00h ce opcode fetch opcode fetch sleep sleep from 007554h q1 bus inactive 0003h 3aabh 0e55h memory cycle instruction execution inst(pc ? 2) sleep mode, movlw 55h from 007556h ? 2007 microchip technology inc. preliminary ds39774c-page 101 pic18f85j11 family 7.7 8-bit data width mode in 8-bit data width mode, the external memory bus operates only in multiplexed mode; that is, data shares the 8 least significant bits of the address bus. figure 7-6 shows an example of 8-bit multiplexed mode for 80-pin devices. this mode is used for a single 8-bit memory connected for 16-bit operation. the instructions will be fetched as two 8-bit bytes on a shared data/address bus. the two bytes are sequen- tially fetched within one instruction cycle (t cy ). therefore, the designer must choose external memory devices according to timing calculations based on 1/2 t cy (2 times the instruction rate). for proper mem- ory speed selection, glue logic propagation delay times must be considered, along with setup and hold times. the address latch enable (ale) pin indicates that the address bits, ad<15:0>, are available on the external memory interface bus. the output enable signal (oe ) will enable one byte of program memory for a portion of the instruction cycle, then ba0 will change and the second byte will be enabled to form the 16-bit instruc- tion word. the least significant bit of the address, ba0, must be connected to the memory devices in this mode. the chip enable signal (ce ) is active at any time that the microcontroller accesses external memory, whether reading or writing. it is inactive (asserted high) whenever the device is in sleep mode. this generally includes basic eprom and flash devices. it allows table writes to byte-wide external memories. during a tblwt instruction cycle, the tablat data is presented on the upper and lower bytes of the ad15:ad0 bus. the appropriate level of the ba0 control line is strobed on the lsb of the tblptr. figure 7-6: 8-bit multiplexed mode example ad<7:0> a<19:16> (1) ale d<15:8> 373 a<19:0> a pic18f85j11 family ds39774c-page 102 preliminary ? 2007 microchip technology inc. 7.7.1 8-bit mode timing the presentation of control signals on the external memory bus is different for the various operating modes. typical signal timing diagrams are shown in figure 7-7 and figure 7-8. figure 7-7: external me mory bus timing for tblrd (extended microcontroller mode) figure 7-8: external memory bus timing for sleep (extended microcontroller mode) q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe ad<7:0> ce opcode fetch opcode fetch opcode fetch tblrd * tblrd cycle 1 addlw 55h from 000100h q2 q1 q3 q4 0ch 33h tblrd 92h from 199e67h 92h from 000104h memory cycle instruction execution inst(pc ? 2) tblrd cycle 2 movlw 55h from 000102h movlw ad<15:8> cfh q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe aah ad<7:0> 00h 00h ce opcode fetch opcode fetch sleep sleep from 007554h q1 bus inactive 00h abh 55h memory cycle instruction execution inst(pc ? 2) sleep mode, movlw 55h from 007556h ad<15:8> 3ah 3ah 03h 0eh ba0 ? 2007 microchip technology inc. preliminary ds39774c-page 103 pic18f85j11 family 7.8 operation in power-managed modes in alternate, power-managed run modes, the external bus continues to operate normally. if a clock source with a lower speed is selected, bus operations will run at that speed. in these cases, excessive access times for the external memory may result if wait states have been enabled and added to external memory opera- tions. if operations in a lower power run mode are anticipated, users should provide in their applications for adjusting memory access times at the lower clock speeds. in sleep and idle modes, the microcontroller core does not need to access data; bus operations are suspended. the state of the external bus is frozen, with the address/data pins and most of the control pins hold- ing at the same state they were in when the mode was invoked. the only potential changes are the ce , lb and ub pins, which are held at logic high. pic18f85j11 family ds39774c-page 104 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. preliminary ds39774c-page 105 pic18f85j11 family 8.0 8 x 8 hardware multiplier 8.1 introduction all pic18 devices include an 8 x 8 hardware multiplier as part of the alu. the multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, prodh:prodl. the multiplier?s operation does not affect any flags in the status register. making multiplication a hardware operation allows it to be completed in a single instruction cycle. this has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the pic18 devices to be used in many applica- tions previously reserved for digital signal processors. a comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in table 8-1. 8.2 operation example 8-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. only one instruction is required when one of the arguments is already loaded in the wreg register. example 8-2 shows the sequence to do an 8 x 8 signed multiplication. to account for the sign bits of the argu- ments, each argument?s most significant bit (msb) is tested and the appropriate subtractions are done. example 8-1: 8 x 8 unsigned multiply routine example 8-2: 8 x 8 signed multiply routine table 8-1: performance comparison for various multiply operations movf arg1, w ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl movf arg1, w mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg1 movf arg2, w btfsc arg1, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg2 routine multiply method program memory (words) cycles (max) time @ 40 mhz @ 10 mhz @ 4 mhz 8 x 8 unsigned without hardware multiply 13 69 6.9 s 27.6 s 69 s hardware multiply 1 1 100 ns 400 ns 1 s 8 x 8 signed without hardware multiply 33 91 9.1 s 36.4 s 91 s hardware multiply 6 6 600 ns 2.4 s 6 s 16 x 16 unsigned without hardware multiply 21 242 24.2 s 96.8 s 242 s hardware multiply 28 28 2.8 s 11.2 s 28 s 16 x 16 signed without hardware multiply 52 254 25.4 s 102.6 s 254 s hardware multiply 35 40 4.0 s 16.0 s 40 s pic18f85j11 family ds39774c-page 106 preliminary ? 2007 microchip technology inc. example 8-3 shows the sequence to do a 16 x 16 unsigned multiplication. equation 8-1 shows the algorithm that is used. the 32-bit result is stored in four registers (res3:res0). equation 8-1: 16 x 16 unsigned multiplication algorithm example 8-3: 16 x 16 unsigned multiply routine example 8-4 shows the sequence to do a 16 x 16 signed multiply. equation 8-2 shows the algorithm used. the 32-bit result is stored in four registers (res3:res0). to account for the sign bits of the arguments, the msb for each argument pair is tested and the appropriate subtractions are done. equation 8-2: 16 x 16 signed multiplication algorithm example 8-4: 16 x 16 signed multiply routine res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) movf arg1l, w mulwf arg2l ; arg1l * arg2l-> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h-> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h-> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l-> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) + (-1 ? arg2h<7> ? arg1h:arg1l ? 2 16 ) + (-1 ? arg1h<7> ? arg2h:arg2l ? 2 16 ) movf arg1l, w mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; btfss arg2h, 7 ; arg2h:arg2l neg? bra sign_arg1 ; no, check arg1 movf arg1l, w ; subwf res2 ; movf arg1h, w ; subwfb res3 ; sign_arg1 btfss arg1h, 7 ; arg1h:arg1l neg? bra cont_code ; no, done movf arg2l, w ; subwf res2 ; movf arg2h, w ; subwfb res3 ; cont_code : ? 2007 microchip technology inc. preliminary ds39774c-page 107 pic18f85j11 family 9.0 interrupts members of the pic18f85j11 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high priority level or a low priority level. the high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. high priority inter- rupt events will interrupt any low priority interrupts that may be in progress. there are thirteen registers which are used to control interrupt operation. these registers are: ? rcon ?intcon ? intcon2 ? intcon3 ? pir1, pir2, pir3 ? pie1, pie2, pie3 ? ipr1, ipr2, ipr3 it is recommended that the microchip header files supplied with mplab ? ide be used for the symbolic bit names in these registers. this allows the assembler/compiler to automatically take care of the placement of these bits within the specified register. in general, interrupt sources have three bits to control their operation. they are: ? flag bit to indicate that an interrupt event occurred ? enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set ? priority bit to select high priority or low priority the interrupt priority feature is enabled by setting the ipen bit (rcon<7>). when interrupt priority is enabled, there are two bits which enable interrupts globally. setting the gieh bit (intcon<7>) enables all interrupts that have the priority bit set (high priority). setting the giel bit (intcon<6>) enables all interrupts that have the priority bit cleared (low priority). when the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. individual interrupts can be disabled through their corresponding enable bits. when the ipen bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with pic ? mcu mid-range devices. in compatibility mode, the interrupt priority bits for each source have no effect. intcon<6> is the peie bit which enables/disables all peripheral interrupt sources. intcon<7> is the gie bit which enables/disables all interrupt sources. all interrupts branch to address 0008h in compatibility mode. when an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. if the ipen bit is cleared, this is the gie bit. if interrupt priority levels are used, this will be either the gieh or giel bit. high priority interrupt sources can interrupt a low priority interrupt. low priority interrupts are not processed while high priority interrupts are in progress. the return address is pushed onto the stack and the pc is loaded with the interrupt vector address (0008h or 0018h). once in the interrupt service routine (isr), the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. the ?return from interrupt? instruction, retfie , exits the interrupt routine and sets the gie bit (gieh or giel if priority levels are used) which re-enables interrupts. for external interrupt events, such as the intx pins or the portb input change interrupt, the interrupt latency will be three to four instruction cycles. the exact latency is the same for one or two-cycle instructions. individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the gie bit. note: do not use the movff instruction to modify any of the interrupt control registers while any interrupt is enabled. doing so may cause erratic microcontroller behavior. pic18f85j11 family ds39774c-page 108 preliminary ? 2007 microchip technology inc. figure 9-1: pic18f85j11 family interrupt logic tmr0ie gie/gieh peie/giel wake-up if in interrupt to cpu vector to location 0008h int2if int2ie int2ip int1if int1ie int1ip tmr0if tmr0ie tmr0ip rbif rbie rbip ipen tmr0if tmr0ip int1if int1ie int1ip int2if int2ie int2ip rbif rbie rbip int0if int0ie peie/giel interrupt to cpu vector to location ipen ipen 0018h pir1<6:3,1:0> pie1<6:3,1:0> ipr1<6:3,1:0> high priority interrupt generation low priority interrupt generation idle or sleep modes gie/gieh int3if int3ie int3ip int3if int3ie int3ip pir2<7:6,3:1> pie2<7:6 3:1> ipr2<7:6,3:1> pir3<6:4,2:1> pie3<6:4,2:1> ipr3<6:4,2:1> pir1<6:3,1:0> pie1<6:3,1:0> ipr1<6:3, 1 :0> pir2<7:6,3:1> pie2<7:6,3:1> ipr2<7:6, 3 : 1 > pir3<6:4,2:1> pie3<6:4,2:1> ipr3<6:4, 2 :1> ipen ? 2007 microchip technology inc. preliminary ds39774c-page 109 pic18f85j11 family 9.1 intcon registers the intcon registers are readable and writable registers which contain various enable, priority and flag bits. note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. register 9-1: intcon: interrupt control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gie/gieh: global interrupt enable bit when ipen = 0 : 1 = enables all unmasked interrupts 0 = disables all interrupts when ipen = 1 : 1 = enables all high priority interrupts 0 = disables all interrupts bit 6 peie/giel: peripheral interrupt enable bit when ipen = 0 : 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts when ipen = 1 : 1 = enables all low priority peripheral interrupts 0 = disables all low priority peripheral interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 overflow interrupt 0 = disables the tmr0 overflow interrupt bit 4 int0ie: int0 external interrupt enable bit 1 = enables the int0 external interrupt 0 = disables the int0 external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 int0if: int0 external interrupt flag bit 1 = the int0 external interrupt occurred (must be cleared in software) 0 = the int0 external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit (1) 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state note 1: a mismatch condition will continue to set this bit. reading portb will end the mismatch condition and allow the bit to be cleared. pic18f85j11 family ds39774c-page 110 preliminary ? 2007 microchip technology inc. register 9-2: intcon2: interrupt control register 2 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rbpu : portb pull-up enable bit 1 = all portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg0: external interrupt 0 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 5 intedg1: external interrupt 1 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 4 intedg2: external interrupt 2 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 3 intedg3: external interrupt 3 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 2 tmr0ip: tmr0 overflow interrupt priority bit 1 =high priority 0 = low priority bit 1 int3ip: int3 external interrupt priority bit 1 =high priority 0 = low priority bit 0 rbip: rb port change interrupt priority bit 1 =high priority 0 = low priority note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. ? 2007 microchip technology inc. preliminary ds39774c-page 111 pic18f85j11 family register 9-3: intcon3: interrupt control register 3 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 int2ip: int2 external interrupt priority bit 1 =high priority 0 = low priority bit 6 int1ip: int1 external interrupt priority bit 1 =high priority 0 = low priority bit 5 int3ie: int3 external interrupt enable bit 1 = enables the int3 external interrupt 0 = disables the int3 external interrupt bit 4 int2ie: int2 external interrupt enable bit 1 = enables the int2 external interrupt 0 = disables the int2 external interrupt bit 3 int1ie: int1 external interrupt enable bit 1 = enables the int1 external interrupt 0 = disables the int1 external interrupt bit 2 int3if: int3 external interrupt flag bit 1 = the int3 external interrupt occurred (must be cleared in software) 0 = the int3 external interrupt did not occur bit 1 int2if: int2 external interrupt flag bit 1 = the int2 external interrupt occurred (must be cleared in software) 0 = the int2 external interrupt did not occur bit 0 int1if: int1 external interrupt flag bit 1 = the int1 external interrupt occurred (must be cleared in software) 0 = the int1 external interrupt did not occur note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. pic18f85j11 family ds39774c-page 112 preliminary ? 2007 microchip technology inc. 9.2 pir registers the pir registers contain the individual flag bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt request (flag) registers (pir1, pir2, pir3). note 1: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit, gie (intcon<7>). 2: user software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. register 9-4: pir1: peripheral interrupt request (flag) register 1 r/w-0 r/w-0 r-0 r-0 r/w-0 u-0 r/w-0 r/w-0 pspif adif rc1if tx1if sspif ?tmr2iftmr1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 pspif: parallel slave port read/write interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred bit 6 adif: a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5 rc1if: eusart receive interrupt flag bit 1 = the eusart receive buffer, rcreg1, is full (cleared when rcreg1 is read) 0 = the eusart receive buffer is empty bit 4 tx1if: eusart transmit interrupt flag bit 1 = the eusart transmit buffer, txreg1, is empty (cleared when txreg1 is written) 0 = the eusart transmit buffer is full bit 3 sspif: master synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2 unimplemented: read as ? 0 ? bit 1 tmr2if: tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow ? 2007 microchip technology inc. preliminary ds39774c-page 113 pic18f85j11 family register 9-5: pir2: peripheral interrupt request (flag) register 2 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 oscfif cmif ? ?bcliflvdiftmr3if ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 oscfif: oscillator fail interrupt flag bit 1 = device oscillator failed, clock input has changed to intosc (must be cleared in software) 0 = device clock operating bit 6 cmif: comparator interrupt flag bit 1 = comparator input has changed (must be cleared in software) 0 = comparator input has not changed bit 5-4 unimplemented: read as ? 0 ? bit 3 bclif: bus collision interrupt flag bit 1 = a bus collision occurred (must be cleared in software) 0 = no bus collision occurred bit 2 lvdif: low-voltage detect interrupt flag bit 1 = a low-voltage condition occurred (must be cleared in software) 0 = the device voltage is above the regulator?s low-voltage trip point bit 1 tmr3if: tmr3 overflow interrupt flag bit 1 = tmr3 register overflowed (must be cleared in software) 0 = tmr3 register did not overflow bit 0 unimplemented: read as ? 0 ? pic18f85j11 family ds39774c-page 114 preliminary ? 2007 microchip technology inc. register 9-6: pir3: peripheral interrupt request (flag) register 3 u-0 u-0 r-0 r-0 u-0 r/w-0 r/w-0 u-0 ? ?rc2iftx2if ? ccp2if ccp1if ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5 rc2if: ausart receive interrupt flag bit 1 = the ausart receive buffer, rcreg2, is full (cleared when rcreg2 is read) 0 = the ausart receive buffer is empty bit 4 tx2if: ausart transmit interrupt flag bit 1 = the ausart transmit buffer, txreg2, is empty (cleared when txreg2 is written) 0 = the ausart transmit buffer is full bit 3 unimplemented: read as ? 0 ? bit 2 ccp2if: ccp2 interrupt flag bit capture mode: 1 = a tmr1/tmr3 register capture occurred (must be cleared in software) 0 = no tmr1/tmr3 register capture occurred compare mode: 1 = a tmr1/tmr3 register compare match occurred (must be cleared in software) 0 = no tmr1/tmr3 register compare match occurred pwm mode: unused in this mode. bit 1 ccp1if: ccp1 interrupt flag bit capture mode: 1 = a tmr1/tmr3 register capture occurred (must be cleared in software) 0 = no tmr1/tmr3 register capture occurred compare mode: 1 = a tmr1/tmr3 register compare match occurred (must be cleared in software) 0 = no tmr1/tmr3 register compare match occurred pwm mode: unused in this mode. bit 0 unimplemented: read as ? 0 ? ? 2007 microchip technology inc. preliminary ds39774c-page 115 pic18f85j11 family 9.3 pie registers the pie registers contain the individual enable bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt enable registers (pie1, pie2, pie3). when ipen = 0 , the peie bit must be set to enable any of these peripheral interrupts. register 9-7: pie1: peripheral interrupt enable register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 pspie adie rc1ie tx1ie sspie ? tmr2ie tmr1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 pspie: parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6 adie: a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5 rc1ie: eusart receive interrupt enable bit 1 = enables the eusart receive interrupt 0 = disables the eusart receive interrupt bit 4 tx1ie: eusart transmit interrupt enable bit 1 = enables the eusart transmit interrupt 0 = disables the eusart transmit interrupt bit 3 sspie: master synchronous serial port interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 2 unimplemented: read as ? 0 ? bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie: tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt pic18f85j11 family ds39774c-page 116 preliminary ? 2007 microchip technology inc. register 9-8: pie2: peripheral interrupt enable register 2 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 oscfie cmie ? ? bclie lvdie tmr3ie ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 oscfie: oscillator fail interrupt enable bit 1 = enabled 0 = disabled bit 6 cmie: comparator interrupt enable bit 1 = enabled 0 = disabled bit 5-4 unimplemented: read as ? 0 ? bit 3 bclie: bus collision interrupt enable bit 1 = enabled 0 = disabled bit 2 lvdie: low-voltage detect interrupt enable bit 1 = enabled 0 = disabled bit 1 tmr3ie: tmr3 overflow interrupt enable bit 1 = enabled 0 = disabled bit 0 unimplemented: read as ? 0 ? ? 2007 microchip technology inc. preliminary ds39774c-page 117 pic18f85j11 family register 9-9: pie3: peripheral interrupt enable register 3 u-0 u-0 r-0 r-0 u-0 r/w-0 r/w-0 u-0 ? ? rc2ie tx2ie ? ccp2ie ccp1ie ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5 rc2ie: ausart receive interrupt enable bit 1 = enabled 0 = disabled bit 4 tx2ie: ausart transmit interrupt enable bit 1 = enabled 0 = disabled bit 3 unimplemented: read as ? 0 ? bit 2 ccp2ie: ccp2 interrupt enable bit 1 = enabled 0 = disabled bit 1 ccp1ie: ccp1 interrupt enable bit 1 = enabled 0 = disabled bit 0 unimplemented: read as ? 0 ? pic18f85j11 family ds39774c-page 118 preliminary ? 2007 microchip technology inc. 9.4 ipr registers the ipr registers contain the individual priority bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt priority registers (ipr1, ipr2, ipr3). using the priority bits requires that the interrupt priority enable (ipen) bit be set. register 9-10: ipr1: peripheral interrupt priority register 1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 u-0 r/w-1 r/w-1 pspip adip rc1ip tx1ip sspip ? tmr2ip tmr1ip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 pspip: parallel slave port read/write interrupt priority bit 1 =high priority 0 = low priority bit 6 adip: a/d converter interrupt priority bit 1 =high priority 0 = low priority bit 5 rc1ip: eusart receive interrupt priority bit 1 =high priority 0 = low priority bit 4 tx1ip: eusart transmit interrupt priority bit 1 =high priority 0 = low priority bit 3 sspip: master synchronous serial port interrupt priority bit 1 =high priority 0 = low priority bit 2 unimplemented: read as ? 0 ? bit 1 tmr2ip: tmr2 to pr2 match interrupt priority bit 1 =high priority 0 = low priority bit 0 tmr1ip: tmr1 overflow interrupt priority bit 1 =high priority 0 = low priority ? 2007 microchip technology inc. preliminary ds39774c-page 119 pic18f85j11 family register 9-11: ipr2: peripheral interrupt priority register 2 r/w-1 r/w-1 u-0 u-0 r/w-1 r/w-1 r/w-1 u-0 oscfip cmip ? ? bclip lvdip tmr3ip ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 oscfip: oscillator fail interrupt priority bit 1 =high priority 0 = low priority bit 6 cmip: comparator interrupt priority bit 1 =high priority 0 = low priority bit 5-4 unimplemented: read as ? 0 ? bit 3 bclip: bus collision interrupt priority bit 1 =high priority 0 = low priority bit 2 lvdip: low-voltage detect interrupt priority bit 1 =high priority 0 = low priority bit 1 tmr3ip: tmr3 overflow interrupt priority bit 1 =high priority 0 = low priority bit 0 unimplemented: read as ? 0 ? pic18f85j11 family ds39774c-page 120 preliminary ? 2007 microchip technology inc. register 9-12: ipr3: peripheral interrupt priority register 3 u-0 u-0 r-0 r-0 u-0 r/w-1 r/w-1 u-0 ? ? rc2ip tx2ip ? ccp2ip ccp1ip ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5 rc2ip: ausart receive priority flag bit 1 =high priority 0 = low priority bit 4 tx2ip: ausart transmit interrupt priority bit 1 =high priority 0 = low priority bit 3 unimplemented: read as ? 0 ? bit 2 ccp2ip: ccp2 interrupt priority bit 1 =high priority 0 = low priority bit 1 ccp1ip: ccp1 interrupt priority bit 1 =high priority 0 = low priority bit 0 unimplemented: read as ? 0 ? ? 2007 microchip technology inc. preliminary ds39774c-page 121 pic18f85j11 family 9.5 rcon register the rcon register contains bits used to determine the cause of the last reset or wake-up from idle or sleep modes. rcon also contains the bit that enables interrupt priorities (ipen). register 9-13: rcon: reset control register r/w-0 u-0 r/w-1 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen ?cm ri to pd por bor bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6 unimplemented: read as ? 0 ? bit 5 cm : configuration mismatch flag bit for details of bit operation, see register 4-1. bit 4 ri : reset instruction flag bit for details of bit operation, see register 4-1. bit 3 to : watchdog timer time-out flag bit for details of bit operation, see register 4-1. bit 2 pd : power-down detection flag bit for details of bit operation, see register 4-1. bit 1 por : power-on reset status bit for details of bit operation, see register 4-1. bit 0 bor : brown-out reset status bit for details of bit operation, see register 4-1. pic18f85j11 family ds39774c-page 122 preliminary ? 2007 microchip technology inc. 9.6 intx pin interrupts external interrupts on the rb0/int0, rb1/int1, rb2/int2 and rb3/int3 pins are edge-triggered. if the corresponding intedgx bit in the intcon2 register is set (= 1 ), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. when a valid edge appears on the rbx/intx pin, the corresponding flag bit, intxif, is set. this interrupt can be disabled by clearing the corresponding enable bit, intxie. flag bit, intxif, must be cleared in software in the interrupt service routine before re-enabling the interrupt. all external interrupts (int0, int1, int2 and int3) can wake-up the processor from the power-managed modes if bit intxie was set prior to going into the power-managed modes. if the global interrupt enable bit, gie, is set, the processor will branch to the interrupt vector following wake-up. interrupt priority for int1, int2 and int3 is determined by the value contained in the interrupt priority bits, int1ip (intcon3<6>), int2ip (intcon3<7>) and int3ip (intcon2<1>). there is no priority bit associated with int0. it is always a high priority interrupt source. 9.7 tmr0 interrupt in 8-bit mode (which is the default), an overflow in the tmr0 register (ffh 00h) will set flag bit, tmr0if. in 16-bit mode, an overflow in the tmr0h:tmr0l register pair (ffffh 0000h) will set tmr0if. the interrupt can be enabled/disabled by setting/clearing enable bit, tmr0ie (intcon<5>). interrupt priority for timer0 is determined by the value contained in the interrupt priority bit, tmr0ip (intcon2<2>). see section 11.0 ?timer0 module? for further details on the timer0 module. 9.8 portb interrupt-on-change an input change on portb<7:4> sets flag bit, rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit, rbie (intcon<3>). interrupt priority for portb interrupt-on-change is determined by the value contained in the interrupt priority bit, rbip (intcon2<0>). 9.9 context saving during interrupts during interrupts, the return pc address is saved on the stack. additionally, the wreg, status and bsr registers are saved on the fast return stack. if a fast return from interrupt is not used (see section 5.3 ?data memory organization? ), the user may need to save the wreg, status and bsr registers on entry to the interrupt service routine. depending on the user?s application, other registers may also need to be saved. example 9-1 saves and restores the wreg, status and bsr registers during an interrupt service routine. example 9-1: saving status, wreg and bsr registers in ram movwf w_temp ; w_temp is in virtual bank movff status, status_temp ; status_temp located anywhere movff bsr, bsr_temp ; bsr_tmep located anywhere ; ; user isr code ; movff bsr_temp, bsr ; restore bsr movf w_temp, w ; restore wreg movff status_temp, status ; restore status ? 2007 microchip technology inc. preliminary ds39774c-page 123 pic18f85j11 family 10.0 i/o ports depending on the device selected and features enabled, there are up to nine ports available. some pins of the i/o ports are multiplexed with an alternate function from the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. each port has three memory mapped registers for its operation: ? tris register (data direction register) ? port register (reads the levels on the pins of the device) ? lat register (output latch register) reading the port register reads the current status of the pins, whereas writing to the port register writes to the output latch (lat) register. setting a tris bit (= 1 ) makes the corresponding port pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a tris bit (= 0 ) makes the corresponding port pin an output (i.e., put the contents of the corresponding lat bit on the selected pin). the output latch (lat register) is useful for read-modify-write operations on the value that the i/o pins are driving. read-modify-write operations on the lat register read and write the latched output value for the port register. a simplified model of a generic i/o port, without the interfaces to other peripherals, is shown in figure 10-1. figure 10-1: generic i/o port operation 10.1 i/o port pin capabilities when developing an application, the capabilities of the port pins must be considered. outputs on some pins have higher output drive strength than others. similarly, some pins can tolerate higher than v dd input levels. 10.1.1 input pins and voltage considerations the voltage tolerance of pins used as device inputs is dependent on the pin?s input function. pins that are used as digital only inputs are able to handle dc voltages up to 5.5v, a level typical for digital logic circuits. in contrast, pins that also have analog input functions of any kind can only tolerate voltages up to v dd . voltage excursions beyond v dd on these pins should be avoided. table 10-1 summarizes the input voltage capabilities. refer to section 25.0 ?electrical characteristics? for more details. table 10-1: input voltage tolerance 10.1.2 pin output drive when used as digital i/o, the output pin drive strengths vary for groups of pins intended to meet the needs for a variety of applications. in general, there are three classes of output pins in terms of drive capability. portb and portc, as well as porta<7:6>, are designed to drive higher current loads, such as leds. portd, porte and portj are capable of driving digital circuits associated with external memory devices. they can also drive leds, but only those with smaller current requirements. portf, portg and porth, along with porta<5:0>, have the lowest drive level, but are capable of driving normal digital circuit loads with a high input impedance. table 10-2 summarizes the output capabilities of the ports. refer to the ?absolute maximum ratings? in section 25.0 ?electrical characteristics? for more details. data bus wr lat wr tris rd port data latch tris latch rd tris input buffer i/o pin (1) q d ck q d ck en q d en rd lat or port note 1: i/o pins have diode protection to v dd and v ss . port or pin tolerated input description porta<7:0> v dd only v dd input levels tolerated. portc<1:0> portf<7:1> portb<7:0> 5.5v tolerates input levels above v dd , useful for most standard logic. portc<7:2> portd<7:0> porte<7:0> portg<4:0> porth<7:0> (1) portj<7:0> (1) note 1: not available on 64-pin devices. pic18f85j11 family ds39774c-page 124 preliminary ? 2007 microchip technology inc. table 10-2: output drive levels for various ports 10.1.3 pull-up configuration four of the i/o ports (portb, portd, porte and portj) implement configurable weak pull-ups on all pins. these are internal pull-ups that allow floating digital input signals to be pulled to a consistent level without the use of external resistors. the pull-ups are enabled with a single bit for each of the ports: rbpu (intcon2<7>) for portb, and rdpu, repu and rjpu (portg<7:5>) for the other ports. 10.1.4 open-drain outputs the output pins for several peripherals are also equipped with a configurable open-drain output option. this allows the peripherals to communicate with external digital logic, operating at a higher voltage level, without the use of level translators. the open-drain option is implemented on port pins specifically associated with the data and clock outputs of the usarts, the mssp module (in spi mode) and the ccp modules. the option is selectively enabled by setting the open-drain control bit for the corresponding module in trisg and latg. their configuration is dis- cussed in more detail in the sections for portc, porte and portg. when the open-drain option is required, the output pin must also be tied through an external pull-up resistor provided by the user to a higher voltage level, up to 5v (figure 10-2). when a digital logic high signal is output, it is pulled up to the higher voltage level. figure 10-2: using the open-drain output (usarts shown as examples 10.2 porta, trisa and lata registers porta is an 8-bit wide, bidirectional port. the corre- sponding data direction and output latch registers are trisa and lata. ra4/t0cki is a schmitt trigger input. all other porta pins have ttl input levels and full cmos output drivers. the ra4 pin is multiplexed with the timer0 clock input. ra5 and ra3:ra0 are multiplexed with analog inputs for the a/d converter. the operation of the analog inputs as a/d converter inputs is selected by clearing or setting the pcfg3:pcfg0 control bits in the adcon1 register. the corresponding trisa bits control the direction of these pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. ra6/osc2/clko and ra7/osc1/clki normally serve as the external circuit connections for the exter- nal (primary) oscillator circuit (hs oscillator modes), or the external clock input and output (ec oscillator modes). in these cases, ra6 and ra7 are not available as digital i/o and their corresponding tris and lat bits are read as ? 0 ?. when the device is configured to use intosc or intrc as the default oscillator mode (fosc2 configuration bit is ? 0 ?), ra6 and ra7 are automatically configured as digital i/o; the oscillator and clock in/clock out functions are disabled. example 10-1: initializing porta low medium high porta<5:0> portd porta<7:6> portf porte portb portg portj (1) portc porth (1) note 1: not available on 64-pin devices. tx x pic18f85j11 +5v 3.3v (at logic ? 1 ?) 3.3v v dd 5v note: ra5 and ra3:ra0 are configured as analog inputs on any reset and are read as ? 0 ?. ra4 is configured as a digital input. clrf porta ; initialize porta by ; clearing output latches clrf lata ; alternate method to ; clear output data latches movlw 07h ; configure a/d movwf adcon1 ; for digital inputs movlw 0bfh ; value used to initialize ; data direction movwf trisa ; set ra<7, 5:0> as inputs, ; ra<6> as output ? 2007 microchip technology inc. preliminary ds39774c-page 125 pic18f85j11 family table 10-3: porta functions table 10-4: summary of registers associated with porta pin name function tris setting i/o i/o type description ra0/an0 ra0 0 o dig lata<0> data output; not affected by analog input. 1 i ttl porta<0> data input; disabled when analog input enabled. an0 1 i ana a/d input channel 0. default input configuration on por; does not affect digital output. ra1/an1 ra1 0 o dig lata<1> data output; not affected by analog input. 1 i ttl porta<1> data input; disabled when analog input enabled. an1 1 i ana a/d input channel 1. default input configuration on por; does not affect digital output. ra2/an2/v ref -ra2 0 o dig lata<2> data output; not affected by analog input. 1 i ttl porta<2> data input. disabled when analog functions enabled. an2 1 i ana a/d input channel 2. default input configuration on por. v ref - 1 i ana a/d and comparator low reference voltage input. ra3/an3/ v ref + ra3 0 o dig lata<3> data output; not affected by analog input. 1 i ttl porta<3> data input; disabled when analog input enabled. an3 1 i ana a/d input channel 3. default input configuration on por. v ref + 1 i ana a/d and comparator high reference voltage input. ra4/t0cki ra4 0 o dig lata<4> data output. 1 i st porta<4> data input; default configuration on por. t0cki x i st timer0 clock input. ra5/an4 ra5 0 o dig lata<5> data output; not affected by analog input. 1 i ttl porta<5> data input; disabled when analog input enabled. an4 1 i ana a/d input channel 4. default configuration on por. ra6/osc2/ clko ra6 0 o dig lata<6> data output; disabled when fosc2 configuration bit is set. 1 i ttl porta<6> data input; disabled when fosc2 configuration bit is set. osc2 x o ana main oscillator feedback output connection (hs and hspll modes). clko x o dig system cycle clock output, f osc /4 (ec and ecpll modes). ra7/osc1/ clki ra7 0 o dig lata<7> data output; disabled when fosc2 configuration bit is set. 1 i ttl porta<7> data input; disabled when fosc2 configuration bit is set. osc1 x i ana main oscillator input connection (hs and hspll modes). clki x i ana main external clock source input (ec and ecpll modes). legend: o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page porta ra7 (1) ra6 (1) ra5 ra4 ra3 ra2 ra1 ra0 54 lata lata7 (1) lata6 (1) lata5 lata4 lata3 lata2 lata1 lata0 54 trisa trisa7 (1) trisa6 (1) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 54 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 53 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by porta. x = don?t care. note 1: these bits are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read as ? x ?. pic18f85j11 family ds39774c-page 126 preliminary ? 2007 microchip technology inc. 10.3 portb, trisb and latb registers portb is an 8-bit wide, bidirectional port. the corre- sponding data direction and output latch registers are trisb and latb. all pins on portb are digital only and tolerate voltages up to 5.5v. each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is performed by clearing bit rbpu (intcon2<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. four of the portb pins (rb7:rb4) have an interrupt-on-change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt-on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?mismatch? outputs of rb7:rb4 are ored together to generate the rb port change interrupt with flag bit, rbif (intcon<0>). this interrupt can wake the device from power-managed modes. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb (except with the movff (any), portb instruction). this will end the mismatch condition. b) clear flag bit, rbif. a mismatch condition will continue to set flag bit, rbif. reading portb will end the mismatch condition and allow flag bit, rbif, to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. example 10-2: initializing portb clrf portb ; initialize portb by ; clearing output ; data latches clrf latb ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs ? 2007 microchip technology inc. preliminary ds39774c-page 127 pic18f85j11 family table 10-5: portb functions table 10-6: summary of registers associated with portb pin name function tris setting i/o i/o type description rb0/int0 rb0 0 o dig latb<0> data output. 1 i ttl portb<0> data input; weak pull-up when rbpu bit is cleared. int0 1 i st external interrupt 0 input. rb1/int1 rb1 0 o dig latb<1> data output. 1 i ttl portb<1> data input; weak pull-up when rbpu bit is cleared. int1 1 i st external interrupt 1 input. rb2/int2 rb2 0 o dig latb<2> data output. 1 i ttl portb<2> data input; weak pull-up when rbpu bit is cleared. int2 1 i st external interrupt 2 input. rb3/int3/ ccp2 rb3 0 o dig latb<3> data output. 1 i ttl portb<3> data input; weak pull-up when rbpu bit is cleared. int3 1 i st external interrupt 3 input. ccp2 (1) 0 o dig ccp2 compare output and ccp2 pwm output; takes priority over port data. 1 i st ccp2 capture input. rb4/kbi0 rb4 0 o dig latb<4> data output. 1 i ttl portb<4> data input; weak pull-up when rbpu bit is cleared. kbi0 i ttl interrupt-on-pin change. rb5/kbi1 rb5 0 o dig latb<5> data output. 1 i ttl portb<5> data input; weak pull-up when rbpu bit is cleared. kbi1 i ttl interrupt-on-pin change. rb6/kbi2/pgc rb6 0 o dig latb<6> data output. 1 i ttl portb<6> data input; weak pull-up when rbpu bit is cleared. kbi2 1 i ttl interrupt-on-pin change. pgc x i st serial execution (icsp?) clock input for icsp and icd operation. (2) rb7/kbi3/pgd rb7 0 o dig latb<7> data output. 1 i ttl portb<7> data input; weak pull-up when rbpu bit is cleared. kbi3 1 i ttl interrupt-on-pin change. pgd x o dig serial execution data output for icsp and icd operation. (2) x i st serial execution data input for icsp and icd operation. (2) legend: o = output, i = input, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: alternate assignment for ccp2 when t he ccp2mx configuration bit is clear ed (extended microcontroller mode, 80-pin devices only). default assignment is rc1. 2: all other pin functions are dis abled when icsp? or icd is enabled. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 54 latb latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 54 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 54 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip 51 intcon3 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if 51 legend: shaded cells are not used by portb. pic18f85j11 family ds39774c-page 128 preliminary ? 2007 microchip technology inc. 10.4 portc, trisc and latc registers portc is an 8-bit wide, bidirectional port. the corre- sponding data direction and output latch registers are trisc and latc. only portc pins, rc2 through rc7, are digital only pins and can tolerate input voltages up to 5.5v. portc is multiplexed with ccp, mssp and eusart peripheral functions (table 10-7). the pins have schmitt trigger input buffers. the pins for ccp, spi and eusart are also configurable for open-drain out- put whenever these functions are active. open-drain configuration is selected by setting the spiod, ccpxod and u1od control bits (trisg<7:5> and latg<6>, respectively). rc1 is normally configured as the default peripheral pin for the ccp2 module. assignment of ccp2 is con- trolled by configuration bit, ccp2mx (default state, ccp2mx = 1 ). when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. the user should refer to the corresponding peripheral section for the correct tris bit settings. the contents of the trisc register are affected by peripheral overrides. reading trisc always returns the current contents, even though a peripheral device may be overriding one or more of the pins. example 10-3: initializing portc note: these pins are configured as digital inputs on any device reset. clrf portc ; initialize portc by ; clearing output ; data latches clrf latc ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs ? 2007 microchip technology inc. preliminary ds39774c-page 129 pic18f85j11 family table 10-7: portc functions pin name function tris setting i/o i/o type description rc0/t1oso/ t13cki rc0 0 o dig latc<0> data output. 1 i st portc<0> data input. t1oso x o ana timer1 oscillator output; enabled when timer1 oscillator enabled. disables digital i/o. t13cki 1 i st timer1/timer3 counter input. rc1/t1osi/ ccp2 rc1 0 o dig latc<1> data output. 1 i st portc<1> data input. t1osi x i ana timer1 oscillator input; enabled when timer1 oscillator enabled. disables digital i/o. ccp2 (1) 0 o dig ccp2 compare output and ccp2 pwm output; takes priority over port data. 1 i st ccp2 capture input. rc2/ccp1 rc2 0 o dig latc<2> data output. 1 i st portc<2> data input. ccp1 0 o dig ccp1 compare output and ccp1 pwm output; takes priority over port data. 1 i st ccp1 capture input. rc3/sck/scl rc3 0 o dig latc<3> data output. 1 i st portc<3> data input. sck 0 o dig spi clock output (mssp module); takes priority over port data. 1 i st spi clock input (mssp module). scl 0 odigi 2 c? clock output (mssp module); takes priority over port data. 1 isti 2 c clock input (mssp module); input type depends on module setting. rc4/sdi/sda rc4 0 o dig latc<4> data output. 1 i st portc<4> data input. sdi 1 i st spi data input (mssp module). sda 1 odigi 2 c data output (mssp module); takes priority over port data. 1 isti 2 c data input (mssp module); input type depends on module setting. rc5/sdo rc5 0 o dig latc<5> data output. 1 i st portc<5> data input. sdo 0 o dig spi data output (mssp module); takes priority over port data. rc6/tx1/ck1 rc6 0 o dig latc<6> data output. 1 i st portc<6> data input. tx1 1 o dig synchronous serial data output (eusart module); takes priority over port data. ck1 1 o dig synchronous serial data input (eus art module). user must configure as an input. 1 i st synchronous serial clock input (eusart module). rc7/rx1/dt1 rc7 0 o dig latc<7> data output. 1 i st portc<7> data input. rx1 1 i st asynchronous serial receive data input (eusart module). dt1 1 o dig synchronous serial data output (eusart module); takes priority over port data. 1 i st synchronous serial data input (eus art module). user must configure as an input. legend: o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: default assignment for ccp2 when ccp2mx configuration bit is set. pic18f85j11 family ds39774c-page 130 preliminary ? 2007 microchip technology inc. table 10-8: summary of registers associated with portc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 54 latc latc7 latbc6 latc5 latcb4 latc3 latc2 latc1 latc0 54 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 54 latg u2od u1od ? latg4 latg3 latg2 latg1 latg0 54 trisg spiod ccp2od ccp1od trisg4 trisg3 trisg2 trisg1 trisg0 54 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by portc. ? 2007 microchip technology inc. preliminary ds39774c-page 131 pic18f85j11 family 10.5 portd, trisd and latd registers portd is an 8-bit wide, bidirectional port. the corre- sponding data direction and output latch registers are trisd and latd. all pins on portd are digital only and tolerate voltages up to 5.5v. all pins on portd are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. each of the portd pins has a weak internal pull-up. a single control bit can turn off all the pull-ups. this is performed by setting bit rdpu (portg<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on all device resets. on 80-pin devices, portd is multiplexed with the system bus as part of the external memory interface. i/o port and other functions are only available when the interface is disabled, by setting the ebdis bit (memcon<7>). when the interface is enabled, portd is the low-order byte of the multiplexed address/data bus (ad7:ad0). the trisd bits are also overridden. portd can also be configured to function as an 8-bit wide, parallel microprocessor port by setting the pspmode control bit (pspcon<4>). in this mode, parallel port data takes priority over other digital i/o (but not the external memory interface). when the parallel port is active, the input buffers are ttl. for more information, refer to section 10.11 ?parallel slave port? . example 10-4: initializing portd note: these pins are configured as digital inputs on any device reset. clrf portd ; initialize portd by ; clearing output ; data latches clrf latd ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisd ; set rd<3:0> as inputs ; rd<5:4> as outputs ; rd<7:6> as inputs pic18f85j11 family ds39774c-page 132 preliminary ? 2007 microchip technology inc. table 10-9: portd functions pin name function tris setting i/o i/o type description rd0/ad0/psp0 rd0 0 o dig latd<0> data output. 1 i st portd<0> data input. ad0 (2) x o dig external memory interface, address/data bit 0 output. (1) x i ttl external memory interface, data bit 0 input. (1) psp0 o dig psp read output data (latd<0>); takes priority over port data. i ttl psp write data input. rd1/ad1/psp1 rd1 0 o dig latd<1> data output. 1 i st portd<1> data input. ad1 (2) x o dig external memory interface, address/data bit 1 output. (1) x i ttl external memory interface, data bit 1 input. (1) psp1 x o dig psp read output data (latd<1>); takes priority over port data. x i ttl psp write data input. rd2/ad2/psp2 rd2 0 o dig latd<2> data output. 1 i st portd<2> data input. ad2 (2) x o dig external memory interface, address/data bit 2 output. (1) x i ttl external memory interface, data bit 2 input. (1) psp2 x o dig psp read output data (latd<2>); takes priority over port data. x i ttl psp write data input. rd3/ad3/psp3 rd3 0 o dig latd<3> data output. 1 i st portd<3> data input. ad3 (2) x o dig external memory interface, address/data bit 3 output. (1) x i ttl external memory interface, data bit 3 input. (1) psp3 x o dig psp read output data (latd<3>); takes priority over port data. x i ttl psp write data input. rd4/ad4/psp4 rd4 0 o dig latd<4> data output. 1 i st portd<4> data input. ad4 (2) x o dig external memory interface, address/data bit 4 output. (1) x i ttl external memory interface, data bit 4 input. (1) psp4 x o dig psp read output data (latd<4>); takes priority over port data. x i ttl psp write data input. rd5/ad5/psp5 rd5 0 o dig latd<5> data output. 1 i st portd<5> data input. ad5 (2) x o dig external memory interface, address/data bit 5 output. (1) x i ttl external memory interface, data bit 5 input. (1) psp5 x o dig psp read output data (latd<5>); takes priority over port data. x i ttl psp write data input. rd6/ad6/psp6 rd6 0 o dig latd<6> data output. 1 i st portd<6> data input. ad6 (2) x o dig-3 external memory interface, address/data bit 6 output. (1) x i ttl external memory interface, data bit 6 input. (1) psp6 x o dig psp read output data (latd<6>); takes priority over port data. x i ttl psp write data input. legend: o = output, i = input, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: external memory interface i/o takes priority over all other digital and psp i/o. 2: available on 80-pin devices only. ? 2007 microchip technology inc. preliminary ds39774c-page 133 pic18f85j11 family table 10-10: summary of registers associated with portd rd7/ad7/psp7 rd7 0 o dig latd<7> data output. 1 i st portd<7> data input. ad7 (2) x o dig external memory interface, address/data bit 7 output. (1) x i ttl external memory interface, data bit 7 input. (1) psp7 x o dig psp read output data (latd<7>); takes priority over port data. x i ttl psp write data input. table 10-9: portd functions (continued) pin name function tris setting i/o i/o type description legend: o = output, i = input, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: external memory interface i/o takes priority over all other digital and psp i/o. 2: available on 80-pin devices only. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 54 latd latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 54 trisd trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 54 portg rdpu repu rjpu (1) rg4 rg3 rg2 rg1 rg0 54 legend: shaded cells are not used by portd. note 1: unimplemented on 64-pin devices, read as ? 0 ?. pic18f85j11 family ds39774c-page 134 preliminary ? 2007 microchip technology inc. 10.6 porte, trise and late registers porte is an 8-bit wide, bidirectional port. the corre- sponding data direction and output latch registers are trise and late. all pins on porte are digital only and tolerate voltages up to 5.5v. all pins on porte are implemented with schmitt trig- ger input buffers. each pin is individually configurable as an input or output. the re7 pin is also configurable for open-drain output when ccp2 is active on this pin. open-drain configuration is selected by setting the ccp2od control bit (trisg<6>) each of the porte pins has a weak internal pull-up. a single control bit can turn off all the pull-ups. this is performed by setting bit repu (portg<6>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on any device reset. on 80-pin devices, porte is multiplexed with the system bus as part of the external memory interface. i/o port and other functions are only available when the interface is disabled by setting the ebdis bit (memcon<7>). when the interface is enabled, porte is the high-order byte of the multiplexed address/data bus (ad15:ad8). the trise bits are also overridden. when the parallel slave port is active on portd, three of the porte pins (re0, re1 and re2) are configured as digital control inputs for the port. the control functions are summarized in table 10-11. the reconfig- uration occurs automatically when the pspmode control bit (pspcon<4>) is set. users must still make certain the corresponding trise bits are set to configure these pins as digital inputs. re7 can also be configured as the alternate peripheral pin for the ccp2 module. this is done by clearing the ccp2mx configuration bit. example 10-5: initializing porte note: these pins are configured as digital inputs on any device reset. clrf porte ; initialize porte by ; clearing output ; data latches clrf late ; alternate method ; to clear output ; data latches movlw 03h ; value used to ; initialize data ; direction movwf trise ; set re<1:0> as inputs ; re<7:2> as outputs ? 2007 microchip technology inc. preliminary ds39774c-page 135 pic18f85j11 family table 10-11: porte functions pin name function tris setting i/o i/o type description re0/rd /ad8 re0 0 o dig late<0> data output. 1 i st porte<0> data input. rd 1 i ttl parallel slave port read enable control input. ad8 (1) x o dig external memory interface, address/data bit 8 output. (2) x i ttl external memory interface, data bit 8 input. (2) re1/wr /ad9 re1 0 o dig late<1> data output. 1 i st porte<1> data input. wr 1 i ttl parallel slave port write enable control input. ad9 (1) x o dig external memory interface, address/data bit 9 output. (2) x i ttl external memory interface, data bit 9 input. (2) re2/ad10/cs re2 0 o dig late<2> data output. 1 i st porte<2> data input. ad10 (1) x o dig external memory interface, address/data bit 10 output. (2) x i ttl external memory interface, data bit 10 input. (2) cs 1 i ttl parallel slave port chip select control input. re3/ad11 re3 0 o dig late<3> data output. 1 i st porte<3> data input. ad11 (1) x o dig external memory interface, address/data bit 11 output. (2) x i ttl external memory interface, data bit 11 input. (2) re4/ad12 re4 0 o dig late<4> data output. 1 i st porte<4> data input. ad12 (1) x o dig external memory interface, address/data bit 12 output. (2) x i ttl external memory interface, data bit 12 input. (2) re5/ad13 re5 0 o dig late<5> data output. 1 i st porte<5> data input. ad13 (1) x o dig external memory interface, address/data bit 13 output. (2) x i ttl external memory interface, data bit 13 input. (2) re6/ad14 re6 0 o dig late<6> data output. 1 i st porte<6> data input. ad14 (1) x o dig external memory interface, address/data bit 14 output. (2) x i ttl external memory interface, data bit 14 input. (2) re7/ad15/ ccp2 re7 0 o dig late<7> data output. 1 i st porte<7> data input. ad15 (1) x o dig external memory interface, address/data bit 15 output. (2) x i ttl external memory interface, data bit 15 input. (2) ccp2 (3) 0 o dig ccp2 compare output and ccp2 pwm output; takes priority over port data. 1 i st ccp2 capture input. legend: o = output, i = input, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: available on 80-pin devices only. 2: external memory interface i/o takes priority over all other digital and psp i/o. 3: alternate assignment for ccp2 when ccp2mx configurat ion bit is cleared (all devices in microcontroller mode). pic18f85j11 family ds39774c-page 136 preliminary ? 2007 microchip technology inc. table 10-12: summary of registers associated with porte name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page porte re7 re6 re5 re4 re3 re2 re1 re0 54 late late7 late6 late5 late4 late3 late2 late1 late0 54 trise trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 54 portg rdpu repu rjpu (1) rg4 rg3 rg2 rg1 rg0 54 trisg spiod ccp2od ccp1od trisg4 trisg3 trisg2 trisg1 trisg0 54 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by porte. note 1: unimplemented on 64-pin devices, read as ? 0 ?. ? 2007 microchip technology inc. preliminary ds39774c-page 137 pic18f85j11 family 10.7 portf, latf and trisf registers portf is a 7-bit wide, bidirectional port. the corre- sponding data direction and output latch registers are trisf and latf. all pins on portf are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. portf is multiplexed with analog peripheral functions. pins rf1 through rf6 may be used as comparator inputs or outputs by setting the appropriate bits in the cmcon register. to use rf6:rf3 as digital inputs, it is also necessary to turn off the comparators. example 10-6: initializing portf note 1: on device resets, pins rf6:rf1 are configured as analog inputs and are read as ? 0 ?. 2: to configure portf as digital i/o, turn off comparators and set adcon1 value. clrf portf ; initialize portf by ; clearing output ; data latches clrf latf ; alternate method ; to clear output ; data latches movlw 07h ; movwf cmcon ; turn off comparators movlw 0fh; movwf adcon1 ; set portf as digital i/o movlw 0ceh ; value used to ; initialize data ; direction movwf trisf ; set rf3:rf1 as inputs ; rf5:rf4 as outputs ; rf7:rf6 as inputs pic18f85j11 family ds39774c-page 138 preliminary ? 2007 microchip technology inc. table 10-13: portf functions table 10-14: summary of registers associated with portf pin name function tris setting i/o i/o type description rf1/an6/ c2out rf1 0 o dig latf<1> data output; not affected by analog input. 1 i st portf<1> data input; disabled when analog input enabled. an6 1 i ana a/d input channel 6. default configuration on por. c2out 0 o dig comparator 2 output; takes priority over port data. rf2/an7/ c1out rf2 0 o dig latf<2> data output; not affected by analog input. 1 i st portf<2> data input; disabled when analog input enabled. an7 1 i ana a/d input channel 7. default configuration on por. c1out 0 o ttl comparator 1 output; takes priority over port data. rf3/an8 rf3 0 o dig latf<3> data output; not affected by analog input. 1 i st portf<3> data input; disabled when analog input enabled. an8 1 i ana a/d input channel 8 and comparator c2+ input. default input configuration on por; not affected by analog output. rf4/an9 rf4 0 o dig latf<4> data output; not affected by analog input. 1 i st portf<4> data input; disabled when analog input enabled. an9 1 i ana a/d input channel 9 and comparator c2- input. default input configuration on por; does not affect digital output. rf5/an10/ cv ref rf5 0 o dig latf<5> data output; not affected by analog input. disabled when cv ref output enabled. 1 i st portf<5> data input; disabled when analog input enabled. disabled when cv ref output enabled. an10 1 i ana a/d input channel 10 and comparator c1+ input. default input configuration on por. cv ref x o ana comparator voltage reference output . enabling this feature disables digital i/o. rf6/an11 rf6 0 o dig latf<6> data output; not affected by analog input. 1 i st portf<6> data input; disabled when analog input enabled. an11 1 i ana a/d input channel 11 and comparator c1- input. default input configuration on por; does not affect digital output. rf7/an5/ss rf7 0 o dig latf<7> data output. 1 i st portf<7> data input. an5 1 i ana a/d input channel 5. default configuration on por. ss 1 i ttl slave select input for mssp module. legend: o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). name bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 reset values on page portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 ?54 latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 ?54 trisf trisf7trisf6trisf5trisf4trisf3trisf2trisf1 ?54 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 53 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 53 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 53 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by portf. ? 2007 microchip technology inc. preliminary ds39774c-page 139 pic18f85j11 family 10.8 portg, trisg and latg registers portg is a 5-bit wide, bidirectional port. the corre- sponding data direction and output latch registers are trisg and latg. all pins on portg are digital only and tolerate voltages up to 5.5v. when operating as i/o, all portg pins have schmitt trigger input buffers. pins rg1 and rg2 are multi- plexed with the ausart module. the rg1 pin is also configurable for open-drain output when the ausart is active. open-drain configuration is selected by setting the u2od control bit (latg<7>). when enabling peripheral functions, care should be taken in defining tris bits for each portg pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. the user should refer to the corresponding peripheral section for the correct tris bit settings. the pin override value is not loaded into the tris register. this allows read-modify-write of the tris register without concern due to peripheral overrides. although the port itself is only five bits wide, the portg<7:5> bits are still implemented to control the weak pull-ups on the i/o ports associated with portd, porte and portj. setting these bits enables the respective port pull-ups. most of the corresponding trisg and latg bits are implemented as open-drain control bits for ccp1, ccp2 and spi (trisg<7:5>), and the usarts (latg<7:6>). setting these bits configures the output pin for the corresponding peripheral for open-drain operation. latg<5> is not implemented. example 10-7: initializing portg clrf portg ; initialize portg by ; clearing output ; data latches clrf latg ; alternate method ; to clear output ; data latches movlw 04h ; value used to ; initialize data ; direction movwf trisg ; set rg1:rg0 as outputs ; rg2 as input ; rg4:rg3 as inputs pic18f85j11 family ds39774c-page 140 preliminary ? 2007 microchip technology inc. table 10-15: portg functions table 10-16: summary of registers associated with portg pin name function tris setting i/o i/o type description rg0 rg0 0 o dig latg<0> data output. 1 i st portg<0> data input. rg1/tx2/ck2 r21 0 o dig latg<1> data output. 1 i st portg<1> data input. tx2 1 o dig synchronous serial data output (ausart2 module); takes priority over port data. ck2 1 o dig synchronous serial data input (aus art2 module). user must configure as an input. 1 i st synchronous serial clock input (ausart2 module). rg2/rx2/dt2 rg2 0 o dig latg<2> data output. 1 i st portg<2> data input. rx2 1 i st asynchronous serial receive data input (ausart2 module). dt2 1 o dig synchronous serial data output (ausart2 module); takes priority over port data. 1 i st synchronous serial data input (ausart2 module). user must configure as an input. rg3 rg3 0 o dig latg<3> data output. 1 i st portg<3> data input. rg4 rg4 0 o dig latg<4> data output. 1 i st portg<4> data input. legend: o = output, i = input, dig = digital output, st = schmitt buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). name bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 reset values on page portg rdpu repu rjpu (1) rg4 rg3 rg2 rg1 rg0 54 latg u2od u1od ? latg4 latg3 latg2 latg1 latg0 54 trisg spiod ccp2od ccp1od trisg4 trisg3 trisg2 trisg1 trisg0 54 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by portg. note 1: unimplemented on 64-pin devices, read as ? 0 ?. ? 2007 microchip technology inc. preliminary ds39774c-page 141 pic18f85j11 family 10.9 porth, lath and trish registers porth is an 8-bit wide, bidirectional i/o port. the corre- sponding data direction and output latch registers are trish and lath. all pins are digital only and tolerate voltages up to 5.5v. all pins on porth are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. when the external memory interface is enabled, four of the porth pins function as the high-order address lines for the interface. the address output from the interface takes priority over other digital i/o. the corresponding trish bits are also overridden. example 10-8: initializing porth table 10-17: porth functions table 10-18: summary of registers associated with porth note: porth is available only on 80-pin devices. clrf porth ; initialize porth by ; clearing output ; data latches clrf lath ; alternate method ; to clear output ; data latches movlw 0fh ; configure porth as movwf adcon1 ; digital i/o movlw 0cfh ; value used to ; initialize data ; direction movwf trish ; set rh3:rh0 as inputs ; rh5:rh4 as outputs ; rh7:rh6 as inputs pin name function tris setting i/o i/o type description rh0/a16 rh0 0 o dig lath<0> data output. 1 i st porth<0> data input. a16 x o dig external memory interface, address line 16. takes priority over port data. rh1/a17 rh1 0 o dig lath<1> data output. 1 i st porth<1> data input. a17 x o dig external memory interface, address line 17. takes priority over port data. rh2/a18 rh2 0 o dig lath<2> data output. 1 i st porth<2> data input. a18 x o dig external memory interface, address line 18. takes priority over port data. rh3/a19 rh3 0 o dig lath<3> data output. 1 i st porth<3> data input. a19 x o dig external memory interface, address line 19. takes priority over port data. rh4 rh4 0 o dig lath<4> data output. 1 i st porth<4> data input. rh5 rh5 0 o dig lath<5> data output. 1 i st porth<5> data input. rh6 rh6 0 o dig lath<6> data output. 1 i st porth<6> data input. rh7 rh7 0 o dig lath<7> data output. 1 i st porth<7> data input. legend: o = output, i = input, dig = digital output, st = schmitt buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page porth rh7 rh6 rh5 rh4 rh3 rh2 rh1 rh0 54 lath lath7 lath6 lath5 lath4 lath3 lath2 lath1 lath0 54 trish trish7 trish6 trish5 trish4 trish3 trish2 trish1 trish0 54 pic18f85j11 family ds39774c-page 142 preliminary ? 2007 microchip technology inc. 10.10 portj, trisj and latj registers portj is an 8-bit wide, bidirectional port. the corre- sponding data direction and output latch registers are trisj and latj. all pins on portj are digital only and tolerate voltages up to 5.5v. all pins on portj are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. each of the portj pins has a weak internal pull-up. the pull-ups are provided to keep the inputs at a known state for the external memory interface while powering up. a single control bit can turn off all the pull-ups. this is performed by clearing bit, rjpu (portg<5>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on any device reset. when the external memory interface is enabled, all of the portj pins function as control outputs for the interface. this occurs automatically when the interface is enabled by clearing the ebdis control bit (memcon<7>). the trisj bits are also overridden. example 10-9: initializing portj note: portj is available only on 80-pin devices. note: these pins are configured as digital inputs on any device reset. clrf portj ; initialize portj by ; clearing output latches clrf latj ; alternate method ; to clear output latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisj ; set rj3:rj0 as inputs ; rj5:rj4 as output ; rj7:rj6 as inputs ? 2007 microchip technology inc. preliminary ds39774c-page 143 pic18f85j11 family table 10-19: portj functions table 10-20: summary of registers associated with portj pin name function tris setting i/o i/o type description rj0/ale rj0 0 o dig latj<0> data output. 1 i st portj<0> data input. ale x o dig external memory interface address latch enable control output; takes priority over digital i/o. rj1/oe rj1 0 o dig latj<1> data output. 1 i st portj<1> data input. oe x o dig external memory interface output enable control output; takes priority over digital i/o. rj2/wrl rj2 0 o dig latj<2> data output. 1 i st portj<2> data input. wrl x o dig external memory bus write low by te control; takes priority over digital i/o. rj3/wrh rj3 0 o dig latj<3> data output. 1 i st portj<3> data input. wrh x o dig external memory interface write high byte control output; takes priority over digital i/o. rj4/ba0 rj4 0 o dig latj<4> data output. 1 i st portj<4> data input. ba0 x o dig external memory interface byte address 0 control output; takes priority over digital i/o. rj5/ce rj5 0 o dig latj<5> data output. 1 i st portj<5> data input. ce x o dig external memory interface chip enable control output; takes priority over digital i/o. rj6/lb rj6 0 o dig latj<6> data output. 1 i st portj<6> data input. lb x o dig external memory interface lower byte enable control output; takes priority over digital i/o. rj7/ub rj7 0 o dig latj<7> data output. 1 i st portj<7> data input. ub x o dig external memory interface upper byte enable control output; takes priority over digital i/o. legend: o = output, i = input, dig = digital output, st = schmitt buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portj rj7 rj6 rj5 rj4 rj3 rj2 rj1 rj0 54 latj latj7 latj6 latj5 latj4 latj3 latj2 latj1 latj0 54 trisj trisj7 trisj6 trisj5 trisj4 trisj3 trisj2 trisj1 trisj0 54 portg rdpu repu rjpu rg4 rg3 rg2 rg1 rg0 54 legend: shaded cells are not used by portj. pic18f85j11 family ds39774c-page 144 preliminary ? 2007 microchip technology inc. 10.11 parallel slave port portd can also function as an 8-bit wide parallel slave port, or microprocessor port, when control bit pspmode (pspcon<4>) is set. it is asynchronously readable and writable by the external world through rd control input pin, re0/rd , and wr control input pin, re1/wr . the psp can directly interface to an 8-bit micro- processor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit pspmode enables port pin, re0/rd , to be the rd input, re1/wr to be the wr input and re2/cs to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be configured as inputs (set). a write to the psp occurs when both the cs and wr lines are first detected low and ends when either are detected high. the pspif and ibf flag bits are both set when the write ends. a read from the psp occurs when both the cs and rd lines are first detected low. the data in portd is read out and the obf bit is set. if the user writes new data to portd to set obf, the data is immediately read out; however, the obf bit is not set. when either the cs or rd lines are detected high, the portd pins return to the input state and the pspif bit is set. user applications should wait for pspif to be set before servicing the psp. when this happens, the ibf and obf bits can be polled and the appropriate action taken. the timing for the control signals in write and read modes is shown in figure 10-4 and figure 10-5, respectively. figure 10-3: portd and porte block diagram (parallel slave port) note: for 80-pin devices, the parallel slave port is available only in microcontroller mode. data bus wr latd rdx q d ck en q d en rd portd pin one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr note: i/o pin has protection diodes to v dd and v ss . ttl ttl ttl ttl or portd rd latd data latch tris latch ? 2007 microchip technology inc. preliminary ds39774c-page 145 pic18f85j11 family figure 10-4: parallel slave port write waveforms register 10-1: pspcon: parallel slave port control register r-0 r-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ibf obf ibov pspmode ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ibf: input buffer full status bit 1 = a word has been received and is waiting to be read by the cpu 0 = no word has been received bit 6 obf: output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5 ibov: input buffer overflow detect bit 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4 pspmode: parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3-0 unimplemented: read as ? 0 ? q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0> pic18f85j11 family ds39774c-page 146 preliminary ? 2007 microchip technology inc. figure 10-5: parallel slave port read waveforms table 10-21: registers associated with parallel slave port q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0> name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 54 latd latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 54 trisd trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 54 porte re7 re6 re5 re4 re3 re2 re1 re0 54 late late7 late6 late5 late4 late3 late2 late1 late0 54 trise trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 54 pspcon ibf obf ibov pspmode ? ? ? ?53 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir1 pspif adif rc1if tx1if ssp1if ? tmr2if tmr1if 53 pie1 pspie adie rc1ie tx1ie ssp1ie ? tmr2ie tmr1ie 53 ipr1 pspip adip rc1ip tx1ip ssp1ip ? tmr2ip tmr1ip 53 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the parallel slave port. ? 2007 microchip technology inc. preliminary ds39774c-page 147 pic18f85j11 family 11.0 timer0 module the timer0 module incorporates the following features: ? software selectable operation as a timer or counter in both 8-bit or 16-bit modes ? readable and writable registers ? dedicated, 8-bit software programmable prescaler ? selectable clock source (internal or external) ? edge select for external clock ? interrupt on overflow the t0con register (register 11-1) controls all aspects of the module?s operation, including the prescale selection; it is both readable and writable. a simplified block diagram of the timer0 module in 8-bit mode is shown in figure 11-1. figure 11-2 shows a simplified block diagram of the timer0 module in 16-bit mode. register 11-1: t0con: timer0 control register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 tmr0on: timer0 on/off control bit 1 = enables timer0 0 = stops timer0 bit 6 t08bit : timer0 8-bit/16-bit control bit 1 = timer0 is configured as an 8-bit timer/counter 0 = timer0 is configured as a 16-bit timer/counter bit 5 t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clko) bit 4 t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : timer0 prescaler assignment bit 1 = timer0 prescaler is not assigned. timer0 clock input bypasses prescaler. 0 = timer0 prescaler is assigned. timer0 clock input comes from prescaler output. bit 2-0 t0ps2:t0ps0 : timer0 prescaler select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value pic18f85j11 family ds39774c-page 148 preliminary ? 2007 microchip technology inc. 11.1 timer0 operation timer0 can operate as either a timer or a counter. the mode is selected with the t0cs bit (t0con<5>). in timer mode (t0cs = 0 ), the module increments on every clock by default unless a different prescaler value is selected (see section 11.3 ?prescaler? ). if the tmr0 register is written to, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. the counter mode is selected by setting the t0cs bit (= 1 ). in this mode, timer0 increments either on every rising or falling edge of pin ra4/t0cki. the increment- ing edge is determined by the timer0 source edge select bit, t0se (t0con<4>). clearing this bit selects the rising edge. restrictions on the external clock input are discussed below. an external clock source can be used to drive timer0; however, it must meet certain requirements to ensure that the external clock can be synchronized with the internal phase clock (t osc ). there is a delay between synchronization and the onset of incrementing the timer/counter. 11.2 timer0 reads and writes in 16-bit mode tmr0h is not the actual high byte of timer0 in 16-bit mode. it is actually a buffered version of the real high byte of timer0 which is not directly readable nor writ- able (refer to figure 11-2). tmr0h is updated with the contents of the high byte of timer0 during a read of tmr0l. this provides the ability to read all 16 bits of timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. similarly, a write to the high byte of timer0 must also take place through the tmr0h buffer register. the high byte is updated with the contents of tmr0h when a write occurs to tmr0l. this allows all 16 bits of timer0 to be updated at once. figure 11-1: timer0 block diagram (8-bit mode) figure 11-2: timer0 block diagram (16-bit mode) note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. t0cki pin t0se 0 1 1 0 t0cs f osc /4 sync with internal clocks tmr0l (2 t cy delay) internal data bus psa t0ps2:t0ps0 set tmr0if on overflow 3 8 8 programmable prescaler note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. t0cki pin t0se 0 1 1 0 t0cs f osc /4 sync with internal clocks tmr0l (2 t cy delay) internal data bus 8 psa t0ps2:t0ps0 set tmr0if on overflow 3 tmr0 tmr0h high byte 8 8 8 read tmr0l write tmr0l 8 programmable prescaler ? 2007 microchip technology inc. preliminary ds39774c-page 149 pic18f85j11 family 11.3 prescaler an 8-bit counter is available as a prescaler for the timer0 module. the prescaler is not directly readable or writable. its value is set by the psa and t0ps2:t0ps0 bits (t0con<3:0>) which determine the prescaler assignment and prescale ratio. clearing the psa bit assigns the prescaler to the timer0 module. when it is assigned, prescale values from 1:2 through 1:256, in power-of-2 increments, are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf tmr0 , movwf tmr0 , bsf tmr0 , etc.) clear the prescaler count. 11.3.1 switching prescaler assignment the prescaler assignment is fully under software control and can be changed ?on-the-fly? during program execution. 11.4 timer0 interrupt the tmr0 interrupt is generated when the tmr0 register overflows from ffh to 00h in 8-bit mode, or from ffffh to 0000h in 16-bit mode. this overflow sets the tmr0if flag bit. the interrupt can be masked by clearing the tmr0ie bit (intcon<5>). before re-enabling the interrupt, the tmr0if bit must be cleared in software by the interrupt service routine. since timer0 is shut down in sleep mode, the tmr0 interrupt cannot awaken the processor from sleep. table 11-1: registers associated with timer0 note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count but will not change the prescaler assignment. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page tmr0l timer0 register low byte 52 tmr0h timer0 register high byte 52 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 52 trisa trisa7 (1) trisa6 (1) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 54 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by timer0. note 1: ra6/ra7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (fosc2 configuration bit = 0 ); otherwise, they are disabled and these bits read as ? 0 ?. pic18f85j11 family ds39774c-page 150 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. preliminary ds39774c-page 151 pic18f85j11 family 12.0 timer1 module the timer1 timer/counter module incorporates these features: ? software selectable operation as a 16-bit timer or counter ? readable and writable 8-bit registers (tmr1h and tmr1l) ? selectable clock source (internal or external) with device clock or timer1 oscillator internal options ? interrupt on overflow ? reset on ccpx special event trigger ? device clock status flag (t1run) a simplified block diagram of the timer1 module is shown in figure 12-1. a block diagram of the module?s operation in read/write mode is shown in figure 12-2. the module incorporates its own low-power oscillator to provide an additional clocking option. the timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation. timer1 can also be used to provide real-time clock (rtc) functionality to applications with only a minimal addition of external components and code overhead. timer1 is controlled through the t1con control register (register 12-1). it also contains the timer1 oscillator enable bit (t1oscen). timer1 can be enabled or disabled by setting or clearing control bit, tmr1on (t1con<0>). register 12-1: t1con: ti mer1 control register r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer1 in one 16-bit operation 0 = enables register read/write of timer1 in two 8-bit operations bit 6 t1run: timer1 system clock status bit 1 = device clock is derived from timer1 oscillator 0 = device clock is derived from another source bit 5-4 t1ckps1:t1ckps0: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable bit 1 = timer1 oscillator is enabled 0 = timer1 oscillator is shut off the oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 t1sync : timer1 external clock input synchronization select bit when tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock when tmr1cs = 0 . bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t13cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 =stops timer1 pic18f85j11 family ds39774c-page 152 preliminary ? 2007 microchip technology inc. 12.1 timer1 operation timer1 can operate in one of these modes: ?timer ? synchronous counter ? asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). when tmr1cs is cleared (= 0 ), timer1 increments on every internal instruction cycle (f osc /4). when the bit is set, timer1 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. when timer1 is enabled, the rc1/t1osi and rc0/t1oso/t13cki pins become inputs. this means the values of trisc<1:0> are ignored and the pins are read as ? 0 ?. figure 12-1: timer1 block diagram (8-bit mode) figure 12-2: timer1 block diagram (16-bit read/write mode) t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen (1) f osc /4 internal clock on/off 1 0 2 t1oso/t13cki t1osi 1 0 tmr1on tmr1l set tmr1if on overflow tmr1 high byte clear tmr1 (ccpx special event trigger) timer1 oscillator note 1: when enable bit, t1oscen, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. on/off timer1 timer1 clock input prescaler 1, 2, 4, 8 synchronize detect t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen (1) f osc /4 internal clock 1 0 2 t1oso/t13cki t1osi note 1: when enable bit, t1oscen, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. 1 0 tmr1l internal data bus 8 set tmr1if on overflow tmr1 tmr1h high byte 8 8 8 read tmr1l write tmr1l 8 tmr1on clear tmr1 (ccpx special event trigger) timer1 oscillator on/off timer1 timer1 clock input prescaler 1, 2, 4, 8 synchronize detect ? 2007 microchip technology inc. preliminary ds39774c-page 153 pic18f85j11 family 12.2 timer1 16-bit read/write mode timer1 can be configured for 16-bit reads and writes (see figure 12-2). when the rd16 control bit (t1con<7>) is set, the address for tmr1h is mapped to a buffer register for the high byte of timer1. a read from tmr1l will load the contents of the high byte of timer1 into the timer1 high byte buffer register. this provides the user with the ability to accurately read all 16 bits of timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. a write to the high byte of timer1 must also take place through the tmr1h buffer register. the timer1 high byte is updated with the contents of tmr1h when a write occurs to tmr1l. this allows a user to write all 16 bits to both the high and low bytes of timer1 at once. the high byte of timer1 is not directly readable or writable in this mode. all reads and writes must take place through the timer1 high byte buffer register. writes to tmr1h do not clear the timer1 prescaler. the prescaler is only cleared on writes to tmr1l. 12.3 timer1 oscillator an on-chip crystal oscillator circuit is incorporated between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting the timer1 oscillator enable bit, t1oscen (t1con<3>). the oscillator is a low-power circuit rated for 32 khz crystals. it will continue to run during all power-managed modes. the circuit for a typical lp oscillator is shown in figure 12-3. table 12-1 shows the capacitor selection for the timer1 oscillator. the user must provide a software time delay to ensure proper start-up of the timer1 oscillator. figure 12-3: external components for the timer1 lp oscillator table 12-1: capacitor selection for the timer1 oscillator (2,3,4) 12.3.1 using timer1 as a clock source the timer1 oscillator is also available as a clock source in power-managed modes. by setting the system clock select bits, scs1:scs0 (osccon<1:0>), to ? 01 ?, the device switches to sec_run mode; both the cpu and peripherals are clocked from the timer1 oscillator. if the idlen bit (osccon<7>) is cleared and a sleep instruction is executed, the device enters sec_idle mode. additional details are available in section 3.0 ?power-managed modes? . whenever the timer1 oscillator is providing the clock source, the timer1 system clock status flag, t1run (t1con<6>), is set. this can be used to determine the controller?s current clocking mode. it can also indicate the clock source being currently used by the fail-safe clock monitor. if the fail-safe clock monitor is enabled and the timer1 oscillator fails while providing the clock, polling the t1run bit will indicate whether the clock is being provided by the timer1 oscillator or another source. note: see the notes with table 12-1 for additional information about capacitor selection. c1 c2 xtal pic18f85j11 t1osi t1oso 32.768 khz 27 pf 27 pf oscillator type freq. c1 c2 lp 32.768 khz 27 pf (1) 27 pf (1) note 1: microchip suggests these values as a starting point in validating the oscillator circuit. 2: higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: capacitor values are for design guidance only. pic18f85j11 family ds39774c-page 154 preliminary ? 2007 microchip technology inc. 12.3.2 timer1 oscillator layout considerations the timer1 oscillator circuit draws very little power during operation. due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. the oscillator circuit, shown in figure 12-3, should be located as close as possible to the microcontroller. there should be no circuits passing within the oscillator circuit boundaries other than v ss or v dd . if a high-speed circuit must be located near the oscilla- tor (such as the ccp1 pin in output compare or pwm mode, or the primary oscillator using the osc2 pin), a grounded guard ring around the oscillator circuit, as shown in figure 12-4, may be helpful when used on a single-sided pcb or in addition to a ground plane. figure 12-4: oscillator circuit with grounded guard ring 12.4 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, tmr1if (pir1<0>). this interrupt can be enabled or disabled by setting or clearing the timer1 interrupt enable bit, tmr1ie (pie1<0>). 12.5 resetting timer1 using the ccpx special event trigger if ccp1 or ccp2 is configured to use timer1 and to generate a special event trigger in compare mode (ccpxm3:ccpxm0 = 1011 ), this signal will reset timer3. the trigger from ccp2 will also start an a/d conversion if the a/d module is enabled (see section 15.3.4 ?special event trigger? for more information). the module must be configured as either a timer or a synchronous counter to take advantage of this feature. when used this way, the ccprxh:ccprxl register pair effectively becomes a period register for timer1. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a special event trigger, the write operation will take precedence. 12.6 using timer1 as a real-time clock adding an external lp oscillator to timer1 (such as the one described in section 12.3 ?timer1 oscillator? above) gives users the option to include rtc function- ality to their applications. this is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. when operating in sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate rtc device and battery backup. the application code routine, rtcisr , shown in example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an interrupt service routine. incrementing the tmr1 register pair to overflow triggers the interrupt and calls the routine which increments the seconds counter by one. additional counters for minutes and hours are incremented as the previous counter overflows. since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 khz clock would take 2 seconds. to force the overflow at the required one-second intervals, it is necessary to pre- load it. the simplest method is to set the msb of tmr1h with a bsf instruction. note that the tmr1l register is never preloaded or altered; doing so may introduce cumulative error over many cycles. for this method to be accurate, timer1 must operate in asynchronous mode and the timer1 overflow interrupt must be enabled (pie1<0> = 1 ), as shown in the routine, rtcinit . the timer1 oscillator must also be enabled and running at all times. v dd osc1 v ss osc2 rc0 rc1 rc2 note: not drawn to scale. note: the special event triggers from the ccpx module will not set the tmr1if interrupt flag bit (pir1<0>). ? 2007 microchip technology inc. preliminary ds39774c-page 155 pic18f85j11 family example 12-1: implementing a real-time clock using a timer1 interrupt service table 12-2: registers associated with timer1 as a timer/counter rtcinit movlw 80h ; preload tmr1 register pair movwf tmr1h ; for 1 second overflow clrf tmr1l movlw b?00001111? ; configure for external clock, movwf t1con ; asynchronous operation, external oscillator clrf secs ; initialize timekeeping registers clrf mins ; movlw .12 movwf hours bsf pie1, tmr1ie ; enable timer1 interrupt return rtcisr bsf tmr1h, 7 ; preload for 1 sec overflow bcf pir1, tmr1if ; clear interrupt flag incf secs, f ; increment seconds movlw .59 ; 60 seconds elapsed? cpfsgt secs return ; no, done clrf secs ; clear seconds incf mins, f ; increment minutes movlw .59 ; 60 minutes elapsed? cpfsgt mins return ; no, done clrf mins ; clear minutes incf hours, f ; increment hours movlw .23 ; 24 hours elapsed? cpfsgt hours return ; no, done clrf hours ; reset hours return ; done name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir1 pspif adif rc1if tx1if sspif ? tmr2if tmr1if 53 pie1 pspie adie rc1ie tx1ie sspie ? tmr2ie tmr1ie 53 ipr1 pspip adip rc1ip tx1ip sspip ? tmr2ip tmr1ip 53 tmr1l timer1 register low byte 52 tmr1h timer1 register high byte 52 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 52 legend: shaded cells are not used by the timer1 module. pic18f85j11 family ds39774c-page 156 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. preliminary ds39774c-page 157 pic18f85j11 family 13.0 timer2 module the timer2 module incorporates the following features: ? 8-bit timer and period registers (tmr2 and pr2, respectively) ? readable and writable (both registers) ? software programmable prescaler (1:1, 1:4 and 1:16) ? software programmable postscaler (1:1 through 1:16) ? interrupt on tmr2 to pr2 match ? optional use as the shift clock for the mssp module the module is controlled through the t2con register (register 13-1) which enables or disables the timer and configures the prescaler and postscaler. timer2 can be shut off by clearing control bit, tmr2on (t2con<2>), to minimize power consumption. a simplified block diagram of the module is shown in figure 13-1. 13.1 timer2 operation in normal operation, tmr2 is incremented from 00h on each clock (f osc /4). a 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by-16 prescale options. these are selected by the prescaler control bits, t2ckps1:t2ckps0 (t2con<1:0>). the value of tmr2 is compared to that of the period register, pr2, on each clock cycle. when the two values match, the comparator generates a match signal as the timer output. this signal also resets the value of tmr2 to 00h on the next cycle and drives the output counter/postscaler (see section 13.2 ?timer2 interrupt? ). the tmr2 and pr2 registers are both directly readable and writable. the tmr2 register is cleared on any device reset while the pr2 register initializes at ffh. both the prescaler and postscaler counters are cleared on the following events: ? a write to the tmr2 register ? a write to the t2con register ? any device reset (power-on reset, mclr reset, watchdog timer reset or brown-out reset) tmr2 is not cleared when t2con is written. register 13-1: t2con: ti mer2 control register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-3 t2outps3:t2outps0: timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale ? ? ? 1111 = 1:16 postscale bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0: timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 pic18f85j11 family ds39774c-page 158 preliminary ? 2007 microchip technology inc. 13.2 timer2 interrupt timer2 can also generate an optional device interrupt. the timer2 output signal (tmr2 to pr2 match) pro- vides the input for the 4-bit output counter/postscaler. this counter generates the tmr2 match interrupt flag which is latched in tmr2if (pir1<1>). the interrupt is enabled by setting the tmr2 match interrupt enable bit, tmr2ie (pie1<1>). a range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, t2outps3:t2outps0 (t2con<6:3>). 13.3 timer2 output the unscaled output of tmr2 is available primarily to the ccp modules where it is used as a time base for operations in pwm mode. timer2 can be optionally used as the shift clock source for the mssp module operating in spi mode. additional information is provided in section 16.0 ?master synchronous serial port (mssp) module? . figure 13-1: timer2 block diagram table 13-1: registers associated with timer2 as a timer/counter name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir1 pspif adif rc1if tx1if sspif ?tmr2if tmr1if 53 pie1 pspie adie rc1ie tx1ie sspie ?tmr2ie tmr1ie 53 ipr1 pspip adip rc1ip tx1ip sspip ?tmr2ip tmr1ip 53 tmr2 timer2 register 52 t2con ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 52 pr2 timer2 period register 52 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer2 module. comparator tmr2 output tmr2 postscaler prescaler pr2 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 4 t2outps3:t2outps0 t2ckps1:t2ckps0 set tmr2if internal data bus 8 reset tmr2/pr2 8 8 (to pwm or mssp) match ? 2007 microchip technology inc. preliminary ds39774c-page 159 pic18f85j11 family 14.0 timer3 module the timer3 timer/counter module incorporates these features: ? software selectable operation as a 16-bit timer or counter ? readable and writable 8-bit registers (tmr3h and tmr3l) ? selectable clock source (internal or external) with device clock or timer1 oscillator internal options ? interrupt on overflow ? module reset on ccpx special event trigger a simplified block diagram of the timer3 module is shown in figure 14-1. a block diagram of the module?s operation in read/write mode is shown in figure 14-2. the timer3 module is controlled through the t3con register (register 14-1). it also selects the clock source options for the ccp modules. see section 15.2.2 ?timer1/timer3 mode selection? for more information. register 14-1: t3con: ti mer3 control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer3 in one 16-bit operation 0 = enables register read/write of timer3 in two 8-bit operations bit 6,3 t3ccp2:t3ccp1: timer3 and timer1 to ccpx enable bits 1x = timer3 is the capture/compare clock source for the ccp modules 01 = timer3 is the capture/compare clock source for ccp2; timer1 is the capture/compare clock source for ccp1 00 = timer1 is the capture/compare clock source for the ccp modules bit 5-4 t3ckps1:t3ckps0 : timer3 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 2 t3sync : timer3 external clock input synchronization control bit (not usable if the device clock comes from timer1/timer3.) when tmr3cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr3cs = 0 : this bit is ignored. timer3 uses the internal clock when tmr3cs = 0 . bit 1 tmr3cs: timer3 clock source select bit 1 = external clock input from timer1 oscillator or t13cki (on the rising edge after the first falling edge) 0 = internal clock (f osc /4) bit 0 tmr3on: timer3 on bit 1 = enables timer3 0 = stops timer3 pic18f85j11 family ds39774c-page 160 preliminary ? 2007 microchip technology inc. 14.1 timer3 operation timer3 can operate in one of three modes: ?timer ? synchronous counter ? asynchronous counter the operating mode is determined by the clock select bit, tmr3cs (t3con<1>). when tmr3cs is cleared (= 0 ), timer3 increments on every internal instruction cycle (f osc /4). when the bit is set, timer3 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. as with timer1, the rc1/t1osi and rc0/t1oso/t13cki pins become inputs when the timer1 oscillator is enabled. this means the values of trisc<1:0> are ignored and the pins are read as ? 0 ?. figure 14-1: timer3 block diagram (8-bit mode) figure 14-2: timer3 block diagram (16-bit read/write mode) t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen (1) f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize detect 1 0 2 t1oso/t13cki t1osi 1 0 tmr3on tmr3l set tmr3if on overflow tmr3 high byte timer1 oscillator note 1: when enable bit, t1oscen, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. on/off timer3 ccpx special event trigger ccpx select from t3con<6,3> clear tmr3 timer1 clock input t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen (1) f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize detect 1 0 2 t1oso/t13cki t1osi note 1: when enable bit, t1oscen, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. 1 0 tmr3l internal data bus 8 set tmr3if on overflow tmr3 tmr3h high byte 8 8 8 read tmr1l write tmr1l 8 tmr3on ccpx special event trigger timer1 oscillator on/off timer3 timer1 clock input ccpx select from t3con<6,3> clear tmr3 ? 2007 microchip technology inc. preliminary ds39774c-page 161 pic18f85j11 family 14.2 timer3 16-bit read/write mode timer3 can be configured for 16-bit reads and writes (see figure 14-2). when the rd16 control bit (t3con<7>) is set, the address for tmr3h is mapped to a buffer register for the high byte of timer3. a read from tmr3l will load the contents of the high byte of timer3 into the timer3 high byte buffer register. this provides the user with the ability to accurately read all 16 bits of timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. a write to the high byte of timer3 must also take place through the tmr3h buffer register. the timer3 high byte is updated with the contents of tmr3h when a write occurs to tmr3l. this allows a user to write all 16 bits to both the high and low bytes of timer3 at once. the high byte of timer3 is not directly readable or writable in this mode. all reads and writes must take place through the timer3 high byte buffer register. writes to tmr3h do not clear the timer3 prescaler. the prescaler is only cleared on writes to tmr3l. 14.3 using the timer1 oscillator as the timer3 clock source the timer1 internal oscillator may be used as the clock source for timer3. the timer1 oscillator is enabled by setting the t1oscen (t1con<3>) bit. to use it as the timer3 clock source, the tmr3cs bit must also be set. as previously noted, this also configures timer3 to increment on every rising edge of the oscillator source. the timer1 oscillator is described in section 12.0 ?timer1 module? . 14.4 timer3 interrupt the tmr3 register pair (tmr3h:tmr3l) increments from 0000h to ffffh and overflows to 0000h. the timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, tmr3if (pir2<1>). this interrupt can be enabled or disabled by setting or clearing the timer3 interrupt enable bit, tmr3ie (pie2<1>). 14.5 resetting timer3 using the ccpx special event trigger if ccp1 or ccp2 is configured to use timer3 and to generate a special event trigger in compare mode (ccpxm3:ccpxm0 = 1011 ), this signal will reset timer3. the trigger from ccp2 will also start an a/d conversion if the a/d module is enabled (see section 15.3.4 ?special event trigger? for more information). the module must be configured as either a timer or synchronous counter to take advantage of this feature. when used this way, the ccprxh:ccprxl register pair effectively becomes a period register for timer3. if timer3 is running in asynchronous counter mode, the reset operation may not work. in the event that a write to timer3 coincides with a special event trigger from a ccpx module, the write will take precedence. table 14-1: registers associated with timer3 as a timer/counter note: the special event triggers from the ccpx module will not set the tmr3if interrupt flag bit (pir2<1>). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir2 oscfif cmif ? ? bclif lvdif tmr3if ?53 pie2 oscfie cmie ? ? bclie lvdie tmr3ie ?53 ipr2 oscfip cmip ? ? bclip lvdip tmr3ip ?53 tmr3l timer3 register low byte 53 tmr3h timer3 register high byte 53 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 52 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 53 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer3 module. pic18f85j11 family ds39774c-page 162 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. preliminary ds39774c-page 163 pic18f85j11 family 15.0 capture/compare/pwm (ccp) modules pic18f85j11 family devices have two ccp (capture/compare/pwm) modules, designated ccp1 and ccp2. both modules implement standard capture, compare and pulse-width modulation (pwm) modes. each ccp module contains a 16-bit register which can operate as a 16-bit capture register, a 16-bit compare register or a pwm master/slave duty cycle register. for the sake of clarity, all ccp module operation in the following sections is described with respect to ccp2, but is equally applicable to ccp1. register 15-1: ccpxcon: ccpx control register (ccp1, ccp2 modules) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dcxb1 dcxb0 ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dcxb1:dcxb0 : pwm duty cycle bit 1 and bit 0 for ccpx module capture mode: unused. compare mode : unused. pwm mode: these bits are the two least significant bits (bit 1 and bit 0) of the 10-bit pwm duty cycle. the eight most significant bits (dcx9:dcx2) of the duty cycle are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : ccpx module mode select bits 0000 = capture/compare/pwm disabled (resets ccpx module) 0001 = reserved 0010 = compare mode, toggle output on match (ccpxif bit is set) 0011 = reserved 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode: initialize ccpx pin low; on compare match, force ccpx pin high (ccpxif bit is set) 1001 = compare mode: initialize ccpx pin high; on compare match, force ccpx pin low (ccpxif bit is set) 1010 = compare mode: generate software interrupt on compare match (ccpxif bit is set, ccpx pin reflects i/o state) 1011 = compare mode: special event trigger; reset timer; start a/d conversion on ccpx match (ccpxif bit is set) (1) 11xx =pwm mode note 1: ccpxm3:ccpxm0 = 1011 will only reset timer and not start a/d conversion on ccpx match. pic18f85j11 family ds39774c-page 164 preliminary ? 2007 microchip technology inc. 15.1 ccp module configuration each capture/compare/pwm module is associated with a control register (generically, ccpxcon) and a data register (ccprx). the data register, in turn, is comprised of two 8-bit registers: ccprxl (low byte) and ccprxh (high byte). all registers are both readable and writable. 15.1.1 ccp modules and timer resources the ccp modules utilize timers 1, 2 or 3, depending on the mode selected. timer1 and timer3 are available to modules in capture or compare mode, while timer2 is available for modules in pwm mode. table 15-1: ccpx mode ? timer resource the assignment of a particular timer to a module is determined by the timer to ccpx enable bits in the t3con register (register 14-1). both modules may be active at any given time and may share the same timer resource if they are configured to operate in the same mode (capture/compare or pwm) at the same time. the interactions between the two modules are summarized in table 15-2. depending on the configuration selected, up to four timers may be active at once, with modules in the same configuration (capture/compare or pwm) sharing timer resources. the possible configurations are shown in figure 15-1. 15.1.2 open-drain output option when operating in output mode (i.e., in compare or pwm modes), the drivers for the ccpx pins can be optionally configured as open-drain outputs. this feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor and allows the output to communicate with external circuits without the need for additional level shifters. the open-drain output option is controlled by the ccp2od and ccp1od bits (trisg<6:5>). setting the appropriate bit configures the pin for the corresponding module for open-drain operation. 15.1.3 ccp2 pin assignment the pin assignment for ccp2 (capture input, compare and pwm output) can change, based on device config- uration. the ccp2mx configuration bit determines which pin ccp2 is multiplexed to. by default, it is assigned to rc1 (ccp2mx = 1 ). if the configuration bit is cleared, ccp2 is multiplexed with re7. changing the pin assignment of ccp2 does not automatically change any requirements for configuring the port pin. users must always verify that the appropri- ate tris register is configured correctly for ccp2 operation, regardless of where it is located. figure 15-1: ccpx and timer interconnect configurations ccpx mode timer resource capture compare pwm timer1 or timer3 timer1 or timer3 timer2 tmr1 tmr2 tmr3 ccp2 ccp1 tmr1 tmr2 tmr3 ccp2 ccp1 tmr1 tmr3 tmr2 ccp2 ccp1 t3ccp<2:1> = 00 t3ccp<2:1> = 01 t3ccp<2:1> = 1x timer1 is used for all capture and compare operations for all ccp modules. timer2 is used for pwm operations for all ccp modules. modules may share either timer resource as a common time base. timer1 is used for capture and compare operations for ccp1 and timer 3 is used for ccp2. both the modules use timer2 as a common time base if they are in pwm modes. timer3 is used for all capture and compare operations for all ccp modules. timer2 is used for pwm operations for all ccp modules. modules may share either timer resource as a common time base. ? 2007 microchip technology inc. preliminary ds39774c-page 165 pic18f85j11 family table 15-2: interactions between ccp1 and ccp2 for timer resources ccp1 mode ccp2 mode interaction capture capture each module can use tmr1 or tmr3 as the time base. the time base can be different for each ccp module. capture compare ccp2 can be configured for the special event trigger to reset tmr1 or tmr3 (depending upon which time base is used). automatic a/d conversions on trigger event can also be done. operation of ccp1 could be affected if it is using the same timer as a time base. compare capture ccp1 can be configured for the special event trigger to reset tmr1 or tmr3 (depending upon which time base is used). operation of ccp2 could be affected if it is using the same timer as a time base. compare compare either module can be configured for the special event trigger to reset the time base. automatic a/d conversions on ccp2 trigger event can be done. conflicts may occur if both modules are using the same time base. capture pwm none compare pwm none pwm capture none pwm compare none pwm pwm both pwms will have the same frequency and update rate (tmr2 interrupt). pic18f85j11 family ds39774c-page 166 preliminary ? 2007 microchip technology inc. 15.2 capture mode in capture mode, the ccpr2h:ccpr2l register pair captures the 16-bit value of the tmr1 or tmr3 register when an event occurs on the ccp2 pin (rb3, rc1 or re7, depending on device configuration). an event is defined as one of the following: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge the event is selected by the mode select bits, ccp2m3:ccp2m0 (ccp2con<3:0>). when a capture is made, the interrupt request flag bit, ccp2if (pir3<2>), is set; it must be cleared in software. if another capture occurs before the value in register ccpr2 is read, the old captured value is overwritten by the new captured value. 15.2.1 ccpx pin configuration in capture mode, the appropriate ccpx pin should be configured as an input by setting the corresponding tris direction bit. 15.2.2 timer1/timer3 mode selection the timers that are to be used with the capture feature (timer1 and/or timer3) must be running in timer mode or synchronized counter mode. in asynchronous counter mode, the capture operation may not work. the timer to be used with each ccp module is selected in the t3con register (see section 15.1.1 ?ccp modules and timer resources? ). 15.2.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep the ccp2ie bit (pie3<2>) clear to avoid false interrupts and should clear the flag bit, ccp2if, following any such change in operating mode. 15.2.4 ccp prescaler there are four prescaler settings in capture mode. they are specified as part of the operating mode selected by the mode select bits (ccp2m3:ccp2m0). whenever the ccp2 module is turned off, or the ccp2 module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. example 15-1 shows the recommended method for switching between capture prescalers. this example also clears the prescaler counter and will not generate the ?false? interrupt. example 15-1: changing between capture prescalers figure 15-2: capture mode operat ion block diagram note: if rb3/int3/ccp2, rc1/t1osi/ccp2 or re7/ccp2 is configured as an output, a write to the port can cause a capture condition. clrf ccp2con ; turn ccp module off movlw new_capt_ps ; load wreg with the ; new prescaler mode ; value and ccp on movwf ccp2con ; load ccp2con with ; this value ccpr1h ccpr1l tmr1h tmr1l set ccp1if tmr3 enable q1:q4 ccp1con<3:0> ccp1 pin prescaler 1, 4, 16 and edge detect tmr1 enable t3ccp2 t3ccp2 ccpr2h ccpr2l tmr1h tmr1l set ccp2if tmr3 enable ccp2con<3:0> ccp2 pin prescaler 1, 4, 16 tmr3h tmr3l tmr1 enable t3ccp2 t3ccp1 t3ccp2 t3ccp1 tmr3h tmr3l and edge detect 4 4 4 ? 2007 microchip technology inc. preliminary ds39774c-page 167 pic18f85j11 family 15.3 compare mode in compare mode, the 16-bit ccpr2 register value is constantly compared against either the tmr1 or tmr3 register pair value. when a match occurs, the ccp2 pin can be: ? driven high ? driven low ? toggled (high-to-low or low-to-high) ? remains unchanged (that is, reflects the state of the i/o latch) the action on the pin is based on the value of the mode select bits (ccp2m3:ccp2m0). at the same time, the interrupt flag bit, ccp2if, is set. 15.3.1 ccpx pin configuration the user must configure the ccpx pin as an output by clearing the appropriate tris bit. 15.3.2 timer1/timer3 mode selection timer1 and/or timer3 must be running in timer mode, or synchronized counter mode, if the ccpx module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 15.3.3 software interrupt mode when the generate software interrupt mode is chosen (ccp2m3:ccp2m0 = 1010 ), the ccp2 pin is not affected. only a ccp2 interrupt is generated, if enabled, and the ccp2ie bit is set. 15.3.4 special event trigger both ccp modules are equipped with a special event trigger. this is an internal hardware signal generated in compare mode to trigger actions by other modules. the special event trigger is enabled by selecting the compare special event trigger mode (ccp2m3:ccp2m0 = 1011 ). for either ccp module, the special event trigger resets the timer register pair for whichever timer resource is currently assigned as the module?s time base. this allows the ccprx registers to serve as a programmable period register for either timer. the special event trigger for ccp2 can also start an a/d conversion. in order to do this, the a/d converter must already be enabled. figure 15-3: compare mode operat ion block diagram note: clearing the ccp2con register will force the rb3, rc1 or re7 compare output latch (depending on device configuration) to the default low level. this is not the portb, portc or po rte i/o data latch. note: the special event trigger of ccp1 only resets timer1/timer3 and cannot start an a/d conversion even when the a/d converter is enabled. ccpr1h ccpr1l tmr1h tmr1l comparator q s r output logic special event trigger set ccp1if ccp1 pin tris ccp1con<3:0> output enable tmr3h tmr3l ccpr2h ccpr2l comparator 1 0 t3ccp2 t3ccp1 set ccp2if 1 0 compare 4 (timer1 reset) q s r output logic special event trigger ccp2 pin tris ccp2con<3:0> output enable 4 (timer1/timer3 reset, a/d trigger) match compare match pic18f85j11 family ds39774c-page 168 preliminary ? 2007 microchip technology inc. table 15-3: registers associated with capture, compare, timer1 and timer3 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 rcon ipen ? cm ri to pd por bor 52 pir3 ? ? rc2if tx2if ? ccp2if ccp1if ?53 pie3 ? ? rc2ie tx2ie ? ccp2ie ccp1ie ?53 ipr3 ? ? rc2ip tx2ip ? ccp2ip ccp1ip ?53 pir2 oscfif cmif ? ? bclif lvdif tmr3if ?53 pie2 oscfie cmie ? ? bclie lvdie tmr3ie ?53 ipr2 oscfip cmip ? ? bclip lvdip tmr3ip ?53 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 54 trise trise7 trise6 trise5 trise4 trise3 ? trise1 trise0 54 trisg spiod ccp2od ccp1od trisg4 trisg3 trisg2 trisg1 trisg0 54 tmr1l timer1 register low byte 52 tmr1h timer1 register high byte 52 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 52 tmr3h timer3 register high byte 53 tmr3l timer3 register low byte 53 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 53 ccpr1l capture/compare/pwm register 1 low byte 54 ccpr1h capture/compare/pwm register 1 high byte 54 ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 54 ccpr2l capture/compare/pwm register 2 low byte 55 ccpr2h capture/compare/pwm register 2 high byte 55 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 55 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by capture/compare, timer1 or timer3. ? 2007 microchip technology inc. preliminary ds39774c-page 169 pic18f85j11 family 15.4 pwm mode in pulse-width modulation (pwm) mode, the ccp2 pin produces up to a 10-bit resolution pwm output. since the ccp2 pin is multiplexed with a portb, portc or porte data latch, the appropriate tris bit must be cleared to make the ccp2 pin an output. figure 15-4 shows a simplified block diagram of the ccp1 module in pwm mode. for a step-by-step procedure on how to set up the ccp module for pwm operation, see section 15.4.3 ?setup for pwm operation? . figure 15-4: simplified pwm block diagram a pwm output (figure 15-5) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 15-5: pwm output 15.4.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the following formula: equation 15-1: pwm frequency is defined as 1/[pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ?tmr2 is cleared ? the ccp2 pin is set (exception: if pwm duty cycle = 0%, the ccp2 pin will not be set) ? the pwm duty cycle is latched from ccpr2l into ccpr2h note: clearing the ccp2con register will force the rb3, rc1 or re7 output latch (depending on device configuration) to the default low level. this is not the portb, portc or porte i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 note 1: the 8-bit tmr2 value is concatenated with the 2-bit internal q clock, or 2 bits of the prescaler, to create the 10-bit time base. note: the timer2 postscalers (see section 13.0 ?timer2 module? ) are not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 pwm period = (pr2) + 1] ? 4 ? t osc ? (tmr2 prescale value) pic18f85j11 family ds39774c-page 170 preliminary ? 2007 microchip technology inc. 15.4.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr2l register and to the ccp2con<5:4> bits. up to 10-bit resolution is available. the ccpr2l contains the eight msbs and the ccp2con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr2l:ccp2con<5:4>. the following equation is used to calculate the pwm duty cycle in time: equation 15-2: ccpr2l and ccp2con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr2h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr2h is a read-only register. the ccpr2h register and a 2-bit internal latch are used to double-buffer the pwm duty cycle. this double-buffering is essential for glitchless pwm operation. when the ccpr2h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp2 pin is cleared. the maximum pwm resolution (bits) for a given pwm frequency is given by the equation: equation 15-3: table 15-4: example pwm frequencies and resolutions at 40 mhz pwm duty cycle = (ccpr2l:ccp2con<5:4>) ? t osc ? (tmr2 prescale value) note: if the pwm duty cycle value is longer than the pwm period, the ccp2 pin will not be cleared. f osc f pwm --------------- ?? ?? log 2 () log ----------------------------- b i t s = pwm resolution (max) pwm frequency 2.44 khz 9.77 khz 39.06 khz 156.25 khz 312.50 khz 416.67 khz timer prescaler (1, 4, 16)1641111 pr2 value ffh ffh ffh 3fh 1fh 17h maximum resolution (bits) 14 12 10 8 7 6.58 ? 2007 microchip technology inc. preliminary ds39774c-page 171 pic18f85j11 family 15.4.3 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr2l register and ccp2con<5:4> bits. 3. make the ccp2 pin an output by clearing the appropriate tris bit. 4. set the tmr2 prescale value, then enable timer2 by writing to t2con. 5. configure the ccp2 module for pwm operation. table 15-5: registers associated with pwm and timer2 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 rcon ipen ? cm ri to pd por bor 52 pir1 pspif adif rc1if tx1if sspif ?tmr2if tmr1if 53 pie1 pspie adie rc1ie tx1ie sspie ?tmr2ie tmr1ie 53 ipr1 pspip adip rc1ip tx1ip sspip ?tmr2ip tmr1ip 53 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 54 trise trise7 trise6 trise5 trise4 trise3 ? trise1 trise0 54 trisg spiod ccp2od ccp1od trisg4 trisg3 trisg2 trisg1 trisg0 54 tmr2 timer2 register 52 pr2 timer2 period register 52 t2con ? t2outps3 t2outps2 t2outps1 t2o utps0 tmr2on t2ckps1 t2ckps0 52 ccpr1l capture/compare/pwm register 1 low byte 54 ccpr1h capture/compare/pwm register 1 high byte 54 ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 54 ccpr2l capture/compare/pwm register 2 low byte 55 ccpr2h capture/compare/pwm register 2 high byte 55 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 55 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by pwm or timer2. pic18f85j11 family ds39774c-page 172 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. preliminary ds39774c-page 173 pic18f85j11 family 16.0 master synchronous serial port (mssp) module 16.1 master ssp (mssp) module overview the master synchronous serial port (mssp) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the mssp module can operate in one of two modes: ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c?) - full master mode - slave mode (with general address call) the i 2 c interface supports the following modes in hardware: ?master mode ? multi-master mode ? slave mode 16.2 control registers the mssp module has three associated control registers. these include a status register (sspstat) and two control registers (sspcon1 and sspcon2). the use of these registers and their individual bits differ significantly depending on whether the mssp module is operated in spi or i 2 c mode. additional details are provided under the individual sections. 16.3 spi mode the spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. all four modes of spi are supported. to accomplish communication, typically three pins are used: ? serial data out (sdo) ? rc5/sdo ? serial data in (sdi) ? rc4/sdi/sda ? serial clock (sck) ? rc3/sck/scl additionally, a fourth pin may be used when in a slave mode of operation: ? slave select (ss ) ? rf7/an5/ss figure 16-1 shows the block diagram of the mssp module when operating in spi mode. figure 16-1: mssp block diagram (spi mode) ( ) read write internal data bus sspsr reg sspm3:sspm0 bit 0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to txx/rxx in sspsr tris bit 2 smp:cke sdo sspbuf reg sdi ss sck pic18f85j11 family ds39774c-page 174 preliminary ? 2007 microchip technology inc. 16.3.1 registers the mssp module has four registers for spi mode operation. these are: ? mssp control register 1 (sspcon1) ? mssp status register (sspstat) ? serial receive/transmit buffer register (sspbuf) ? mssp shift register (sspsr) ? not directly accessible sspcon1 and sspstat are the control and status registers in spi mode operation. the sspcon1 register is readable and writable. the lower 6 bits of the sspstat are read-only. the upper two bits of the sspstat are read/write. sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to or read from. in receive operations, sspsr and sspbuf together create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double-buffered. a write to sspbuf will write to both sspbuf and sspsr. register 16-1: sspstat: mssp status register (spi mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r0 r-0 smp cke (1) d/a psr/w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 smp: sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode. bit 6 cke: spi clock select bit (1) 1 = transmit occurs on transition from active to idle clock state 0 = transmit occurs on transition from idle to active clock state bit 5 d/a : data/address bit used in i 2 c? mode only. bit 4 p: stop bit used in i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared. bit 3 s: start bit used in i 2 c mode only. bit 2 r/w : read/write information bit used in i 2 c mode only. bit 1 ua: update address bit used in i 2 c mode only. bit 0 bf: buffer full status bit (receive mode only) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty note 1: polarity of clock state is set by the ckp bit (sspcon1<4>). ? 2007 microchip technology inc. preliminary ds39774c-page 175 pic18f85j11 family register 16-2: sspcon1: mssp control register 1 (spi mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov (1) sspen (2) ckp sspm3 (3) sspm2 (3) sspm1 (3) sspm0 (3) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 wcol: write collision detect bit (transmit mode only) 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit (1) spi slave mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of over- flow, the data in sspsr is lost. overflow can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = no overflow bit 5 sspen: master synchronous serial port enable bit (2) 1 = enables serial port and configures sck, sdo, sdi and ss as serial port pins 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: clock polarity select bit 1 = idle state for clock is a high level 0 = idle state for clock is a low level bit 3-0 sspm3:sspm0: master synchronous serial port mode select bits (3) 0101 = spi slave mode, clock = sck pin, ss pin control disabled, ss can be used as i/o pin 0100 = spi slave mode, clock = sck pin, ss pin control enabled 0011 = spi master mode, clock = tmr2 output/2 0010 = spi master mode, clock = f osc /64 0001 = spi master mode, clock = f osc /16 0000 = spi master mode, clock = f osc /4 note 1: in master mode, the overflow bit is not set, since each new reception (and transmission) is initiated by writing to the sspbuf register. 2: when enabled, this pin must be properly configured as an input or output. 3: bit combinations not specifically listed here are either reserved or implemented in i 2 c? mode only. pic18f85j11 family ds39774c-page 176 preliminary ? 2007 microchip technology inc. 16.3.2 operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspcon1<5:0> and sspstat<7:6>). these control bits allow the following to be specified: ? master mode (sck is the clock output) ? slave mode (sck is the clock input) ? clock polarity (idle state of sck) ? data input sample phase (middle or end of data output time) ? clock edge (output data on rising/falling edge of sck) ? clock rate (master mode only) ? slave select mode (slave mode only) the mssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr until the received data is ready. once the 8 bits of data have been received, that byte is moved to the sspbuf register. then, the buffer full detect bit, bf (sspstat<0>), and the mssp interrupt flag bit, sspif, are set. this double-buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmis- sion/reception of data will be ignored and the write collision detect bit, wcol (sspcon1<7>), will be set. user software must clear the wcol bit so that it can be determined if the following write(s) to the sspbuf register completed successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. the buffer full bit, bf (sspstat<0>), indicates when sspbuf has been loaded with the received data (trans- mission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmission/reception has com- pleted. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 16-1 shows the loading of the sspbuf (sspsr) for data transmission. the sspsr is not directly readable or writable and can only be accessed by addressing the sspbuf register. additionally, the sspstat register indicates the various status conditions. example 16-1: loading the sspbuf (sspsr) register loop btfss sspstat, bf ;has data been received (transmit complete)? bra loop ;no movf sspbuf, w ;wreg reg = contents of sspbuf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf sspbuf ;new data to xmit ? 2007 microchip technology inc. preliminary ds39774c-page 177 pic18f85j11 family 16.3.3 enabling spi i/o to enable the serial port, mssp enable bit, sspen (sspcon1<5>), must be set. to reset or reconfigure spi mode, clear the sspen bit, reinitialize the sspcon registers and then set the sspen bit. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port func- tion, some must have their data direction bits (in the tris register) appropriately programmed as follows: ? sdi is automatically controlled by the spi module ? sdo must have trisc<5> bit cleared ? sck (master mode) must have trisc<3> bit cleared ? sck (slave mode) must have trisc<3> bit set ?ss must have trisf<7> bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. 16.3.4 open-drain output option the drivers for the sdo output and sck clock pins can be optionally configured as open-drain outputs. this feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor, and allows the output to communicate with external circuits without the need for additional level shifters. the open-drain output option is controlled by the spiod bit (trisg<7>). setting the bit configures both pins for open-drain operation. 16.3.5 typical connection figure 16-2 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock. both processors should be programmed to the same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: ? master sends data ? slave sends dummy data ? master sends data ? slave sends data ? master sends dummy data ? slave sends data figure 16-2: spi master/slave connection serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm3:sspm0 = 00xx serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm3:sspm0 = 010x serial clock pic18f85j11 family ds39774c-page 178 preliminary ? 2007 microchip technology inc. 16.3.6 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2, figure 16-2) will broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be dis- abled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ?line activity monitor? mode. the clock polarity is selected by appropriately programming the ckp bit (sspcon1<4>). this, then, would give waveforms for spi communication as shown in figure 16-3, figure 16-5 and figure 16-6, where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user-programmable to be one of the following: ?f osc /4 (or t cy ) ?f osc /16 (or 4 ? t cy ) ?f osc /64 (or 16 ? t cy ) ? timer2 output/2 this allows a maximum data rate (at 40 mhz) of 10.00 mbps. figure 16-3 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 16-3: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 sdi sspif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) next q4 cycle after q2 bit 0 ? 2007 microchip technology inc. preliminary ds39774c-page 179 pic18f85j11 family 16.3.7 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched, the sspif interrupt flag bit is set. before enabling the module in spi slave mode, the clock line must match the proper idle state. the clock line can be observed by reading the sck pin. the idle state is determined by the ckp bit (sspcon1<4>). while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. when a byte is received, the device will wake-up from sleep. 16.3.8 slave select synchronization the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon1<3:0> = 04h). when the ss pin is low, trans- mission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. external pull-up/pull-down resistors may be desirable depending on the application. when the spi module resets, the bit counter is forced to ? 0 ?. this can be done by either forcing the ss pin to a high level or clearing the sspen bit. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver, the sdo pin can be configured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus conflict. figure 16-4: slave synchronization waveform note 1: when the spi is in slave mode with ss pin control enabled (sspcon1<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke set, then the ss pin control must be enabled. sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 7 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag bit 0 bit 7 bit 0 next q4 cycle after q2 pic18f85j11 family ds39774c-page 180 preliminary ? 2007 microchip technology inc. figure 16-5: spi mode waveform (slave mode with cke = 0 ) figure 16-6: spi mode waveform (slave mode with cke = 1 ) sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag optional next q4 cycle after q2 bit 0 sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 1 ) cke = 1 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag not optional next q4 cycle after q2 ? 2007 microchip technology inc. preliminary ds39774c-page 181 pic18f85j11 family 16.3.9 operation in power-managed modes in spi master mode, module clocks may be operating at a different speed than when in full power mode; in the case of sleep mode, all clocks are halted. in idle modes, a clock is provided to the peripherals. that clock should be from the primary clock source, the secondary clock (timer1 oscillator at 32.768 khz) or the intrc source. see section 2.3 ?clock sources and oscillator switching? for additional information. in most cases, the speed that the master clocks spi data is not important; however, this should be evaluated for each system. if mssp interrupts are enabled, they can wake the con- troller from sleep mode, or one of the idle modes, when the master completes sending data. if an exit from sleep or idle mode is not desired, mssp interrupts should be disabled. if the sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the devices wakes. after the device returns to run mode, the module will resume transmitting and receiving data. in spi slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in any power-managed mode and data to be shifted into the spi transmit/receive shift register. when all 8 bits have been received, the mssp interrupt flag bit will be set, and if enabled, will wake the device. 16.3.10 effects of a reset a reset disables the mssp module and terminates the current transfer. 16.3.11 bus mode compatibility table 16-1 shows the compatibility between the standard spi modes and the states of the ckp and cke control bits. table 16-1: spi bus modes there is also an smp bit which controls when the data is sampled. table 16-2: registers associated with spi operation standard spi mode terminology control bits state ckp cke 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir1 pspif adif rc1if tx1if sspif ? tmr2if tmr1if 53 pie1 pspie adie rc1ie tx1ie sspie ? tmr2ie tmr1ie 53 ipr1 pspip adip rc1ip tx1ip sspip ? tmr2ip tmr1ip 53 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 54 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 ?54 trisg spiod ccp2od ccp1od trisg4 trisg3 trisg2 trisg1 trisg0 54 sspbuf mssp receive buffer/transmit register 52 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 52 sspstat smp cke d/a p s r/w ua bf 52 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the mssp module in spi mode. pic18f85j11 family ds39774c-page 182 preliminary ? 2007 microchip technology inc. 16.4 i 2 c mode the mssp module in i 2 c mode fully implements all master and slave functions (including general call support) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master function). the mssp module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. two pins are used for data transfer: ? serial clock (scl) ? rc3/sck/scl ? serial data (sda) ? rc4/sdi/sda the user must configure these pins as inputs by setting the trisc<4:3> bits. figure 16-7: mssp block diagram (i 2 c? mode) 16.4.1 registers the mssp module has six registers for i 2 c operation. these are: ? mssp control register 1 (sspcon1) ? mssp control register 2 (sspcon2) ? mssp status register (sspstat) ? serial receive/transmit buffer register (sspbuf) ? mssp shift register (sspsr) ? not directly accessible ? mssp address register (sspadd) sspcon1, sspcon2 and sspstat are the control and status registers in i 2 c mode operation. the sspcon1 and sspcon2 registers are readable and writable. the lower 6 bits of the sspstat are read-only. the upper two bits of the sspstat are read/write. many of the bits in sspcon2 assume different functions, depending on whether the module is operat- ing in master or slave mode; bits <5:2> also assume different names in slave mode. the different aspects of sspcon2 are shown in register 16-5 (for master mode) and register 16-6 (slave mode). sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to or read from. sspadd register holds the slave device address when the mssp is configured in i 2 c slave mode. when the mssp is configured in master mode, the lower seven bits of sspadd act as the baud rate generator reload value. in receive operations, sspsr and sspbuf together create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double-buffered. a write to sspbuf will write to both sspbuf and sspsr. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) shift clock msb lsb scl sda address mask ? 2007 microchip technology inc. preliminary ds39774c-page 183 pic18f85j11 family register 16-3: sspstat: mssp status register (i 2 c? mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r0 r-0 smp cke d/a p (1) s (1) r/w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 smp: slew rate control bit in master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high-speed mode (400 khz) bit 6 cke: smbus select bit in master or slave mode: 1 = enable smbus specific inputs 0 = disable smbus specific inputs bit 5 d/a : data/address bit in master mode: reserved. in slave mode: 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (1) 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last bit 3 s: start bit (1) 1 = indicates that a start bit has been detected last 0 = start bit was not detected last bit 2 r/w : read/write information bit (i 2 c mode only) in slave mode: (2) 1 = read 0 = write in master mode: (3) 1 = transmit is in progress 0 = transmit is not in progress bit 1 ua: update address bit (10-bit slave mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit in transmit mode: 1 = sspbuf is full 0 = sspbuf is empty in receive mode: 1 = sspbuf is full (does not include the ack and stop bits) 0 = sspbuf is empty (does not include the ack and stop bits) note 1: this bit is cleared on reset and when sspen is cleared. 2: this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit or not ack bit. 3: oring this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in active mode. pic18f85j11 family ds39774c-page 184 preliminary ? 2007 microchip technology inc. register 16-4: sspcon1: mssp control register 1 (i 2 c? mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen (1) ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 wcol: write collision detect bit in master transmit mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started (must be cleared in software) 0 = no collision in slave transmit mode: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision in receive mode (master or slave modes): this is a ?don?t care? bit. bit 6 sspov: receive overflow indicator bit in receive mode: 1 = a byte is received while the sspbuf register is still holding the previous byte (must be cleared in software) 0 = no overflow in transmit mode: this is a ?don?t care? bit in transmit mode. bit 5 sspen: master synchronous serial port enable bit (1) 1 = enables the serial port and configures the sda and scl pins as the serial port pins 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: sck release control bit in slave mode: 1 = release clock 0 = holds clock low (clock stretch), used to ensure data setup time in master mode: unused in this mode. bit 3-0 sspm3:sspm0: synchronous serial port mode select bits 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1011 = i 2 c firmware controlled master mode (slave idle) 1000 = i 2 c master mode, clock = f osc /(4 * (sspadd + 1)) 0111 = i 2 c slave mode, 10-bit address 0110 = i 2 c slave mode, 7-bit address bit combinations not specifically listed here are either reserved or implemented in spi mode only. note 1: when enabled, the sda and scl pins must be configured as inputs. ? 2007 microchip technology inc. preliminary ds39774c-page 185 pic18f85j11 family register 16-5: sspcon2: mssp control register 2 (i 2 c? master mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt (1) acken (2) rcen (2) pen (2) rsen (2) sen (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gcen: general call enable bit unused in master mode. bit 6 ackstat: acknowledge status bit (master transmit mode only) 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5 ackdt: acknowledge data bit (master receive mode only) (1) 1 = not acknowledge 0 = acknowledge bit 4 acken: acknowledge sequence enable bit (2) 1 = initiate acknowledge sequence on sda and scl pins and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (master receive mode only) (2) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (2) 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enable bit (2) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enable bit (2) 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle note 1: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. 2: if the i 2 c module is active, these bits may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled). pic18f85j11 family ds39774c-page 186 preliminary ? 2007 microchip technology inc. register 16-6: sspcon2: mssp control register 2 (i 2 c? slave mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat admsk5 admsk4 admsk3 admsk2 admsk1 sen (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gcen: general call enable bit 1 = enable interrupt when a general call address (0000h) is received in the sspsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit unused in slave mode. bit 5-2 admsk5:admsk2: slave address mask select bits 1 = masking of corresponding bits of sspadd enabled 0 = masking of corresponding bits of sspadd disabled bit 1 admsk1: slave address least significant bit(s) mask select bit in 7- bit address mode: 1 = masking of sspadd<1> only enabled 0 = masking of sspadd<1> only disabled in 10- bit address mode: 1 = masking of sspadd<1:0> enabled 0 = masking of sspadd<1:0> disabled bit 0 sen: stretch enable bit (1) 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is disabled note 1: if the i 2 c module is active, this bit may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled). ? 2007 microchip technology inc. preliminary ds39774c-page 187 pic18f85j11 family 16.4.2 operation the mssp module functions are enabled by setting the mssp enable bit, sspen (sspcon1<5>). the sspcon1 register allows control of the i 2 c operation. four mode selection bits (sspcon1<3:0>) allow one of the following i 2 c modes to be selected: ?i 2 c master mode, clock = (f osc /4) x (sspadd + 1) ?i 2 c slave mode (7-bit address) ?i 2 c slave mode (10-bit address) ?i 2 c slave mode (7-bit address) with start and stop bit interrupts enabled ?i 2 c slave mode (10-bit address) with start and stop bit interrupts enabled ?i 2 c firmware controlled master mode, slave is idle selection of any i 2 c mode, with the sspen bit set, forces the scl and sda pins to be open-drain, provided these pins are programmed to inputs by setting the appropriate trisc or trisd bits. to ensure proper operation of the module, pull-up resistors must be provided externally to the scl and sda pins. 16.4.3 slave mode in slave mode, the scl and sda pins must be configured as inputs (trisc<4:3> set). the mssp module will override the input state with the output data when required (slave-transmitter). the i 2 c slave mode hardware will always generate an interrupt on an exact address match. in addition, address masking will also allow the hardware to gener- ate an interrupt for more than one address (up to 31 in 7-bit addressing and up to 63 in 10-bit addressing). through the mode select bits, the user can also choose to interrupt on start and stop bits. when an address is matched, or the data transfer after an address match is received, the hardware auto- matically will generate the acknowledge (ack ) pulse and load the sspbuf register with the received value currently in the sspsr register. any combination of the following conditions will cause the mssp module not to give this ack pulse: ? the buffer full bit, bf (sspstat<0>), was set before the transfer was received. ? the mssp overflow bit, sspov (sspcon1<6>), was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but the sspif bit is set. the bf bit is cleared by reading the sspbuf register, while the sspov bit is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the mssp module, are shown in timing parameter 100 and parameter 101. 16.4.3.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start condition, the 8 bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is com- pared on the falling edge of the eighth clock (scl) pulse. if the addresses match and the bf and sspov bits are clear, the following events occur: 1. the sspsr register value is loaded into the sspbuf register. 2. the buffer full bit, bf, is set. 3. an ack pulse is generated. 4. the mssp interrupt flag bit, sspif, is set (and the interrupt is generated, if enabled) on the falling edge of the ninth scl pulse. in 10-bit addressing mode, two address bytes need to be received by the slave. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal ? 11110 a9 a8 0 ?, where ? a9 ? and ? a8 ? are the two msbs of the address. the sequence of events for 10-bit addressing is as follows, with steps 7 through 9 for the slave-transmitter: 1. receive first (high) byte of address (bits sspif, bf and ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit, sspif. 4. receive second (low) byte of address (sspif, bf and ua bits are set). 5. update the sspadd register with the first (high) byte of address. if match releases scl line, this will clear ua bit. 6. read the sspbuf register (clears bit bf) and clear flag bit, sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (sspif and bf bits are set). 9. read the sspbuf register (clears bf bit) and clear flag bit, sspif. pic18f85j11 family ds39774c-page 188 preliminary ? 2007 microchip technology inc. 16.4.3.2 address masking masking an address bit causes that bit to become a ?don?t care?. when one address bit is masked, two addresses will be acknowledged and cause an interrupt. it is possible to mask more than one address bit at a time, which makes it possible to acknowledge up to 31 addresses in 7-bit addressing mode and up to 63 addresses in 10-bit addressing mode (see example 16-2). the i 2 c slave behaves the same way, whether address masking is used or not. however, when address masking is used, the i 2 c slave can acknowledge multiple addresses and cause interrupts. when this occurs, it is necessary to determine which address caused the interrupt by checking sspbuf. in 7-bit addressing mode, address mask bits, admsk<5:1> (sspcon2<5:1>), mask the correspond- ing address bits in the sspadd register. for any admsk bits that are set (admsk ? 2007 microchip technology inc. preliminary ds39774c-page 189 pic18f85j11 family 16.4.3.3 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register and the sda line is held low (ack ). when the address byte overflow condition exists, then the no acknowledge (ack ) pulse is given. an overflow condition is defined as either bit, bf (sspstat<0>), is set or bit, sspov (sspcon1<6>), is set. an mssp interrupt is generated for each data transfer byte. the interrupt flag bit, sspif, must be cleared in software. the sspstat register is used to determine the status of the byte. if sen is enabled (sspcon2<0> = 1 ), sck/scl will be held low (clock stretch) following each data transfer. the clock must be released by setting bit, ckp (sspcon1<4>). see section 16.4.4 ?clock stretching? for more details. 16.4.3.4 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit and pin rc3 is held low, regard- less of sen (see section 16.4.4 ?clock stretching? for more details). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspbuf register which also loads the sspsr register. then, pin rc3 should be enabled by setting bit, ckp (sspcon1<4>). the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 16-10). the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. if the sda line is high (not ack ), then the data transfer is complete. in this case, when the ack is latched by the slave, the slave logic is reset (resets sspstat register) and the slave monitors for another occurrence of the start bit. if the sda line was low (ack ), the next transmit data must be loaded into the sspbuf register. again, pin rc3 must be enabled by setting bit, ckp. an mssp interrupt is generated for each data transfer byte. the sspif bit must be cleared in software and the sspstat register is used to determine the status of the byte. the sspif bit is set on the falling edge of the ninth clock pulse. pic18f85j11 family ds39774c-page 190 preliminary ? 2007 microchip technology inc. figure 16-8: i 2 c? slave mode timing with sen = 0 (reception, 7-bit addressing) sda scl sspif (pir1<3>) bf (sspstat<0>) sspov (sspcon1<6>) s 12345678912345678912345 789 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 ckp (sspcon1<4) (ckp does not reset to ? 0 ? when sen = 0 ) ? 2007 microchip technology inc. preliminary ds39774c-page 191 pic18f85j11 family figure 16-9: i 2 c? slave mode timing with sen = 0 and admsk<5:1> = 01011 (reception, 7-bit addressing) sda scl sspif (pir1<3>) bf (sspstat<0>) sspov (sspcon1<6>) s 1 234567 89 12 34567 89 1 2345 7 89 p a7 a6 a5 x a3 x x d7d6d5d4d3d2d1d0 d7d6d5d4d3 d1d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 ckp (sspcon1<4>) (ckp does not reset to ? 0 ? when sen = 0 ) note 1: x = don?t care (i.e., address bit can be either a ? 1 ? or a ? 0 ?). 2: in this example, an address equal to a7.a6.a5.x.a3.x.x will be acknowledged and cause an interrupt. pic18f85j11 family ds39774c-page 192 preliminary ? 2007 microchip technology inc. figure 16-10: i 2 c? slave mode timing (transmission, 7-bit addressing) sda scl bf (sspstat<0>) a6 a5 a4 a3 a2 a1 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software data in sampled s ack transmitting data r/w = 0 ack receiving address a7 d7 9 1 d6 d5 d4 d3 d2 d1 d0 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software from sspif isr transmitting data d7 1 ckp (sspcon1<4>) p ack ckp is set in software ckp is set in software scl held low while cpu responds to sspif sspif (pir1<3>) from sspif isr ? 2007 microchip technology inc. preliminary ds39774c-page 193 pic18f85j11 family figure 16-11: i 2 c? slave mode timing with sen = 0 (reception, 10-bit addressing) sda scl sspif (pir1<3>) bf (sspstat<0>) s 123456789 12 3456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1a0 d7 d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp (sspcon1<4>) 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon1<6>) sspov is set because sspbuf is still full. ack is not sent. (ckp does not reset to ? 0 ? when sen = 0 ) clock is held low until update of sspadd has taken place pic18f85j11 family ds39774c-page 194 preliminary ? 2007 microchip technology inc. figure 16-12: i 2 c? slave mode timing with sen = 0 and admsk<5:1> = 01001 (reception, 10-bit addressing) sda scl sspif (pir1<3>) bf (sspstat<0>) s 123456789 123456789 12345 789 p 1 1 1 1 0 a9 a8 a7 a6 a5 x a3 a2 x x d7 d6 d5 d4 d3 d1 d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp (sspcon1<4>) 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon1<6>) sspov is set because sspbuf is still full. ack is not sent. (ckp does not reset to ? 0 ? when sen = 0 ) clock is held low until update of sspadd has taken place note 1: x = don?t care (i.e., address bit can be either a ? 1 ? or a ? 0 ?). 2: in this example, an address equal to a9.a8.a7.a6.a5.x .a3.a2.x.x will be acknowledged and cause an interrupt. 3: note that the most significant bits of the address are not affected by the bit masking. ? 2007 microchip technology inc. preliminary ds39774c-page 195 pic18f85j11 family figure 16-13: i 2 c? slave mode timing (transmission, 10-bit addressing) sda scl sspif (pir1<3>) bf (sspstat<0>) s 123456789 123456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1a0 11110 a8 r/w = 1 ack ack r/w = 0 ack receive first byte of address cleared in software bus master terminates transfer a9 6 receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address. sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag receive first byte of address 12345 789 d7 d6 d5 d4 d3 d1 ack d2 6 transmitting data byte d0 dummy read of sspbuf to clear bf flag sr cleared in software write of sspbuf initiates transmit cleared in software completion of clears bf flag ckp (sspcon1<4>) ckp is set in software ckp is automatically cleared in hardware, holding scl low clock is held low until update of sspadd has taken place data transmission clock is held low until ckp is set to ? 1 ? third address sequence bf flag is clear at the end of the pic18f85j11 family ds39774c-page 196 preliminary ? 2007 microchip technology inc. 16.4.4 clock stretching both 7-bit and 10-bit slave modes implement automatic clock stretching during a transmit sequence. the sen bit (sspcon2<0>) allows clock stretching to be enabled during receives. setting sen will cause the scl pin to be held low at the end of each data receive sequence. 16.4.4.1 clock stretching for 7-bit slave receive mode (sen = 1 ) in 7-bit slave receive mode when the bf bit is set, on the falling edge of the ninth clock at the end of the ack sequence, the ckp bit in the sspcon1 register is automatically cleared, forcing the scl output to be held low. the ckp bit being cleared to ? 0 ? will assert the scl line low. the ckp bit must be set in the user?s isr before reception is allowed to continue. by holding the scl line low, the user has time to service the isr and read the contents of the sspbuf before the master device can initiate another receive sequence. this will prevent buffer overruns from occurring (see figure 16-15). 16.4.4.2 clock stretching for 10-bit slave receive mode (sen = 1 ) in 10-bit slave receive mode, during the address sequence, clock stretching automatically takes place but the ckp bit is not cleared. during this time, if the ua bit is set after the ninth clock, clock stretching is initiated. the ua bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the r/w bit cleared to ? 0 ?. the release of the clock line occurs upon updating sspadd. clock stretching will occur on each data receive sequence as described in 7-bit mode. 16.4.4.3 clock stretching for 7-bit slave transmit mode the 7-bit slave transmit mode implements clock stretching by clearing the ckp bit after the falling edge of the ninth clock if the bf bit is clear. this occurs regardless of the state of the sen bit. the user?s isr must set the ckp bit before transmis- sion is allowed to continue. by holding the scl line low, the user has time to service the isr and load the contents of the sspbuf before the master device can initiate another transmit sequence (see figure 16-10). 16.4.4.4 clock stretching for 10-bit slave transmit mode in 10-bit slave transmit mode, clock stretching is controlled during the first two address sequences by the state of the ua bit, just as it is in 10-bit slave receive mode. the first two addresses are followed by a third address sequence which contains the high-order bits of the 10-bit address and the r/w bit set to ? 1 ?. after the third address sequence is performed, the ua bit is not set, the module is now configured in transmit mode and clock stretching is controlled by the bf flag as in 7-bit slave transmit mode (see figure 16-13). note 1: if the user reads the contents of the sspbuf before the falling edge of the ninth clock, thus clearing the bf bit, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit. the user should be careful to clear the bf bit in the isr before the next receive sequence in order to prevent an overflow condition. note: if the user polls the ua bit and clears it by updating the sspadd register before the falling edge of the ninth clock occurs and if the user hasn?t cleared the bf bit by read- ing the sspbuf register before that time, then the ckp bit will still not be asserted low. clock stretching on the basis of the state of the bf bit only occurs during a data sequence, not an address sequence. note 1: if the user loads the contents of sspbuf, setting the bf bit before the falling edge of the ninth clock, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit. ? 2007 microchip technology inc. preliminary ds39774c-page 197 pic18f85j11 family 16.4.4.5 clock synchronization and the ckp bit when the ckp bit is cleared, the scl output is forced to ? 0 ?. however, clearing the ckp bit will not assert the scl output low until the scl output is already sam- pled low. therefore, the ckp bit will not assert the scl line until an external i 2 c master device has already asserted the scl line. the scl output will remain low until the ckp bit is set and all other devices on the i 2 c bus have deasserted scl. this ensures that a write to the ckp bit will not violate the minimum high time requirement for scl (see figure 16-14). figure 16-14: clock synchronization timing sda scl dx ? 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspconx ckp master device deasserts clock master device asserts clock pic18f85j11 family ds39774c-page 198 preliminary ? 2007 microchip technology inc. figure 16-15: i 2 c? slave mode timing with sen = 1 (reception, 7-bit addressing) sda scl sspif (pir1<3>) bf (sspstat<0>) sspov (sspcon1<6>) s 1 234 56789 1 2345 67 89 1 2345 7 89 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 ckp (sspcon1<4>) ckp written to ? 1 ? in if bf is cleared prior to the falling edge of the 9th clock, ckp will not be reset to ? 0 ? and no clock stretching will occur software clock is held low until ckp is set to ? 1 ? clock is not held low because buffer full bit is clear prior to falling edge of 9th clock clock is not held low because ack = 1 bf is set after falling edge of the 9th clock, ckp is reset to ? 0 ? and clock stretching occurs ? 2007 microchip technology inc. preliminary ds39774c-page 199 pic18f85j11 family figure 16-16: i 2 c? slave mode timing with sen = 1 (reception, 10-bit addressing) sda scl sspif (pir1<3>) bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 2345 78 9 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 d7d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address after falling edge ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address after falling edge sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp (sspcon1<4>) 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon1<6>) ckp written to ? 1 ? note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. in software clock is held low until update of sspadd has taken place of ninth clock of ninth clock sspov is set because sspbuf is still full. ack is not sent. dummy read of sspbuf to clear bf flag clock is held low until ckp is set to ? 1 ? clock is not held low because ack = 1 pic18f85j11 family ds39774c-page 200 preliminary ? 2007 microchip technology inc. 16.4.5 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually determines which device will be the slave addressed by the master. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all ? 0 ?s with r/w = 0 . the general call address is recognized when the general call enable bit, gcen, is enabled (sspcon2<7> set). following a start bit detect, 8 bits are shifted into the sspsr and the address is compared against the sspadd. it is also compared to the general call address and fixed in hardware. if the general call address matches, the sspsr is transferred to the sspbuf, the bf flag bit is set (eighth bit) and on the falling edge of the ninth bit (ack bit), the sspif interrupt flag bit is set. when the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the sspbuf. the value can be used to determine if the address was device specific or a general call address. in 10-bit addressing mode, the sspadd is required to be updated for the second half of the address to match and the ua bit is set (sspstat<1>). if the general call address is sampled when the gcen bit is set, while the slave is configured in 10-bit addressing mode, then the second half of the address is not necessary, the ua bit will not be set and the slave will begin receiving data after the acknowledge (figure 16-17). figure 16-17: slave mode general call address sequence (7 or 10-bit addressing mode) sda scl s sspif bf (sspstat<0>) sspov (sspcon1<6>) cleared in software sspbuf is read r/w = 0 ack general call address address is compared to general call address; gcen (sspcon2<7>) receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack , set interrupt ? 0 ? ? 1 ? ? 2007 microchip technology inc. preliminary ds39774c-page 201 pic18f85j11 family 16.4.6 master mode master mode is enabled by setting and clearing the appropriate sspm bits in sspcon1 and by setting the sspen bit. in master mode, the scl and sda lines are manipulated by the mssp hardware. master mode of operation is supported by interrupt generation on the detection of the start and stop con- ditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle, with both the s and p bits clear. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit conditions. once master mode is enabled, the user has six options. 1. assert a start condition on sda and scl. 2. assert a repeated start condition on sda and scl. 3. write to the sspbuf register initiating transmission of data/address. 4. configure the i 2 c port to receive data. 5. generate an acknowledge condition at the end of a received byte of data. 6. generate a stop condition on sda and scl. the following events will cause the mssp interrupt flag bit, sspif, to be set (and mssp interrupt, if enabled): ? start condition ? stop condition ? data transfer byte transmitted/received ? acknowledge transmit ? repeated start figure 16-18: mssp block diagram (i 2 c? master mode) note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to initiate transmission before the start con- dition is complete. in this case, the sspbuf will not be written to and the wcol bit will be set, indicating that a write to the sspbuf did not occur. read write sspsr start bit, stop bit, sspbuf internal data bus set/reset s, p, wcol (sspstat, sspcon1); shift clock msb lsb sda acknowledge generate stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif; reset ackstat, pen (sspcon2) rate generator sspm3:sspm0 start bit detect pic18f85j11 family ds39774c-page 202 preliminary ? 2007 microchip technology inc. 16.4.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ?. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address followed by a ? 1 ? to indicate the receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmit- ted. start and stop conditions indicate the beginning and end of transmission. the baud rate generator used for the spi mode operation is used to set the scl clock frequency for either 100 khz, 400 khz or 1 mhz i 2 c operation. see section 16.4.7 ?baud rate? for more detail. a typical transmit sequence would go as follows: 1. the user generates a start condition by setting the start enable bit, sen (sspcon2<0>). 2. sspif is set. the mssp module will wait the required start time before any other operation takes place. 3. the user loads the sspbuf with the slave address to transmit. 4. address is shifted out the sda pin until all 8 bits are transmitted. 5. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 6. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 7. the user loads the sspbuf with eight bits of data. 8. data is shifted out the sda pin until all 8 bits are transmitted. 9. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 10. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 11. the user generates a stop condition by setting the stop enable bit, pen (sspcon2<2>). 12. interrupt is generated once the stop condition is complete. ? 2007 microchip technology inc. preliminary ds39774c-page 203 pic18f85j11 family 16.4.7 baud rate in i 2 c master mode, the baud rate generator (brg) reload value is placed in the lower 7 bits of the sspadd register (figure 16-19). when a write occurs to sspbuf, the baud rate generator will automatically begin counting. the brg counts down to 0 and stops until another reload has taken place. the brg count is decremented twice per instruction cycle (t cy ) on the q2 and q4 clocks. in i 2 c master mode, the brg is reloaded automatically. once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ack ), the internal clock will automatically stop counting and the scl pin will remain in its last state. table 16-3 demonstrates clock rates based on instruction cycles and the brg value loaded into sspadd. 16.4.7.1 baud rate generation in power-managed modes when the device is operating in one of the power-managed modes, the clock source to the brg may change frequency, or even stop, depending on the mode and clock source selected. switching to a run or idle mode from either the secondary clock or internal oscillator is likely to change the clock rate to the brg. in sleep mode, the brg will not be clocked at all. figure 16-19: baud rate generator block diagram table 16-3: i 2 c? clock rate w/brg sspm3:sspm0 brg down counter clko f osc /4 sspadd<6:0> sspm3:sspm0 scl reload control reload f cy f cy * 2 brg value f scl (2 rollovers of brg) 10 mhz 20 mhz 18h 400 khz (1) 10 mhz 20 mhz 1fh 312.5 khz 10 mhz 20 mhz 63h 100 khz 4 mhz 8 mhz 09h 400 khz (1) 4 mhz 8 mhz 0ch 308 khz 4 mhz 8 mhz 27h 100 khz 1 mhz 2 mhz 02h 333 khz (1) 1 mhz 2 mhz 09h 100 khz 1 mhz 2 mhz 00h 1 mhz (1) note 1: the i 2 c? interface does not conform to the 400 khz i 2 c specification (which applies to rates greater than 100 khz) in all details, but may be used with care where higher rates are required by the application. pic18f85j11 family ds39774c-page 204 preliminary ? 2007 microchip technology inc. 16.4.7.2 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, deasserts the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device (figure 16-20). figure 16-20: baud rate generator timing with clock arbitration sda scl scl deasserted but slave holds dx ? 1 dx brg scl is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles ? 2007 microchip technology inc. preliminary ds39774c-page 205 pic18f85j11 family 16.4.8 i 2 c master mode start condition timing to initiate a start condition, the user sets the start enable bit, sen (sspcon2<0>). if the sda and scl pins are sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition and causes the s bit (sspstat<3>) to be set. following this, the baud rate generator is reloaded with the contents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspcon2<0>) will be automatically cleared by hardware. the baud rate generator is suspended, leaving the sda line held low and the start condition is complete. 16.4.8.1 wcol status flag if the user writes the sspbuf when a start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 16-21: first start bit timing note: if, at the beginning of the start condition, the sda and scl pins are already sam- pled low, or if during the start condition, the scl line is sampled low before the sda line is driven low, a bus collision occurs. the bus collision interrupt flag, bclif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. sda scl s t brg 1st bit 2nd bit t brg sda = 1 , at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspstat<3>) and sets sspif bit pic18f85j11 family ds39774c-page 206 preliminary ? 2007 microchip technology inc. 16.4.9 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspcon2<1>) is programmed high and the i 2 c logic module is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded with the contents of sspadd<6:0> and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sda is sampled high, the scl pin will be deasserted (brought high). when scl is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0 ) for one t brg while scl is high. following this, the rsen bit (sspcon2<1>) will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit (sspstat<3>) will be set. the sspif bit will not be set until the baud rate generator has timed out. immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit addressing mode or the default first address in 10-bit addressing mode. after the first eight bits are transmit- ted and an ack is received, the user may then transmit an additional eight bits of address (10-bit addressing mode) or eight bits of data (7-bit addressing mode). 16.4.9.1 wcol status flag if the user writes the sspbuf when a repeated start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 16-22: repeated start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low-to-high. ? scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the repeated start condition is complete. sda scl sr = repeated start write to sspbuf occurs here on falling edge of ninth clock, end of xmit at completion of start bit, hardware clears rsen bit 1st bit s bit set by hardware t brg t brg sda = 1 , sda = 1 , scl (no change) scl = 1 write to sspcon2 occurs here: t brg t brg and sets sspif rsen bit set by hardware t brg ? 2007 microchip technology inc. preliminary ds39774c-page 207 pic18f85j11 family 16.4.10 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the sspbuf register. this action will set the buffer full bit, bf, and allow the baud rate generator to begin counting and start the next trans- mission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time specification parameter 106). scl is held low for one baud rate generator rollover count (t brg ). data should be valid before scl is released high (see data setup time specification parameter 107). when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda. this allows the slave device being addressed to respond with an ack bit during the ninth bit time if an address match occurred, or if data was received properly. the status of ack is written into the ackdt bit on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared; if not, the bit is set. after the ninth clock, the sspif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf, leaving scl low and sda unchanged (figure 16-23). after the write to the sspbuf, each bit of the address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the falling edge of the eighth clock, the master will deassert the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat bit (sspcon2<6>). following the falling edge of the ninth clock transmission of the address, the sspif bit is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to float. 16.4.10.1 bf status flag in transmit mode, the bf bit (sspstat<0>) is set when the cpu writes to sspbuf and is cleared when all 8 bits are shifted out. 16.4.10.2 wcol status flag if the user writes to the sspbuf when a transmit is already in progress (i.e., sspsr is still shifting out a data byte), the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur) after 2t cy after the sspbuf write. if sspbuf is rewritten within 2 t cy , the wcol bit is set and sspbuf is updated. this may result in a corrupted transfer. the user should verify that the wcol is clear after each write to sspbuf to ensure the transfer is correct. in all cases, wcol must be cleared in software. 16.4.10.3 ackstat status flag in transmit mode, the ackstat bit (sspcon2<6>) is cleared when the slave has sent an acknowledge (ack = 0 ) and is set when the slave does not acknowl- edge (ack = 1 ). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 16.4.11 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspcon2<3>). the baud rate generator begins counting, and on each rollover, the state of the scl pin changes (high-to-low/low-to-high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the con- tents of the sspsr are loaded into the sspbuf, the bf flag bit is set, the sspif flag bit is set and the baud rate generator is suspended from counting, holding scl low. the mssp is now in idle state awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable bit, acken (sspcon2<4>). 16.4.11.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when the sspbuf register is read. 16.4.11.2 sspov status flag in receive operation, the sspov bit is set when 8 bits are received into the sspsr and the bf flag bit is already set from a previous reception. 16.4.11.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e., sspsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). note: the mssp module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded. pic18f85j11 family ds39774c-page 208 preliminary ? 2007 microchip technology inc. figure 16-23: i 2 c? master mode waveform (transmission, 7 or 10-bit addressing) sda scl sspif bf sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from mssp interrupt after start condition, sen cleared by hardware s sspbuf written with 7-bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> (sen = 1 ), start condition begins from slave, clear ackstat bit (sspcon2<6>) ackstat in sspcon2 = 1 cleared in software sspbuf written pen r/w cleared in software ? 2007 microchip technology inc. preliminary ds39774c-page 209 pic18f85j11 family figure 16-24: i 2 c? master mode waveform (reception, 7-bit addressing) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 1 23456 789 12345678 9 123 4 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 0 transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1 ), write to sspbuf occurs here, ack from slave master configured as a receiver by programming sspcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sda = 0 , scl = 1 while cpu ack cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif ack from master, set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknowledge sequence of receive set acken, start acknowledge sequence, sda = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspcon2<4> to start acknowledge sequence, sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically acken begin start condition cleared in software sda = ackdt = 0 last bit is shifted into sspsr and contents are unloaded into sspbuf cleared in software sspov is set because sspbuf is still full responds to sspif pic18f85j11 family ds39774c-page 210 preliminary ? 2007 microchip technology inc. 16.4.12 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspcon2<4>). when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit are presented on the sda pin. if the user wishes to gen- erate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the scl pin is deasserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode (figure 16-25). 16.4.12.1 wcol status flag if the user writes the sspbuf when an acknowledge sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). 16.4.13 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen (sspcon2<2>). at the end of a receive/transmit, the scl line is held low after the fall- ing edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sampled low, the baud rate generator is reloaded and counts down to ? 0 ?. when the baud rate generator times out, the scl pin will be brought high and one t brg (baud rate generator rollover count) later, the sda pin will be deasserted. when the sda pin is sampled high while scl is high, the p bit (sspstat<4>) is set. a t brg later, the pen bit is cleared and the sspif bit is set (figure 16-26). 16.4.13.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 16-25: acknowledge sequence waveform figure 16-26: stop cond ition receive or transmit mode note: t brg = one baud rate generator period. sda scl sspif set at acknowledge sequence starts here, write to sspcon2, acken automatically cleared cleared in t brg t brg the end of receive 8 acken = 1 , ackdt = 0 d0 9 sspif software sspif set at the end of acknowledge sequence cleared in software ack scl sda sda asserted low before rising edge of clock write to sspcon2, set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat<4>) is set. t brg to setup stop condition ack p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set ? 2007 microchip technology inc. preliminary ds39774c-page 211 pic18f85j11 family 16.4.14 sleep operation while in sleep mode, the i 2 c module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 16.4.15 effects of a reset a reset disables the mssp module and terminates the current transfer. 16.4.16 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspstat<4>) is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the mssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be monitored for arbitration to see if the signal level is the expected output level. this check is performed in hardware with the result placed in the bclif bit. the states where arbitration can be lost are: ? address transfer ? data transfer ? a start condition ? a repeated start condition ? an acknowledge condition 16.4.17 multi -master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a ? 1 ? on sda by letting sda float high, and another master asserts a ? 0 ?. when the scl pin floats high, data should be stable. if the expected data on sda is a ? 1 ? and the data sampled on the sda pin = 0 , then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif and reset the i 2 c port to its idle state (figure 16-27). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are deasserted and the sspbuf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are deasserted and the respective control bits in the sspcon2 register are cleared. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register, or the bus is idle and the s and p bits are cleared. figure 16-27: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high, data doesn?t match what is driven bus collision has occurred. set bus collision interrupt (bclif) by the master. by master data changes while scl = 0 pic18f85j11 family ds39774c-page 212 preliminary ? 2007 microchip technology inc. 16.4.17.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition (figure 16-28). b) scl is sampled low before sda is asserted low (figure 16-29). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: ? the start condition is aborted; ? the bclif flag is set; and ? the mssp module is reset to its idle state (figure 16-28). the start condition begins with the sda and scl pins deasserted. when the sda pin is sampled high, the baud rate generator is loaded from sspadd<6:0> and counts down to 0. if the scl pin is sampled low while sda is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early (figure 16-30). if, however, a ? 1 ? is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to 0. if the scl pin is sampled as ? 0 ? during this time, a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 16-28: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus colli- sion because the two masters must be allowed to arbitrate the first address following the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because mssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1 , scl = 1 sda = 0 , scl = 1 . bclif sspif sda = 0 , scl = 1 . sspif and bclif are cleared in software sspif and bclif are cleared in software set bclif, start condition. set bclif. s ? 2007 microchip technology inc. preliminary ds39774c-page 213 pic18f85j11 family figure 16-29: bus collision d uring start condition (scl = 0 ) figure 16-30: brg reset due to sda arbitrat ion during start condition sda scl sen bus collision occurs. set bclif. scl = 0 before sda = 0 , set sen, enable start sequence if sda = 1 , scl = 1 t brg t brg sda = 0 , scl = 1 bclif s sspif interrupt cleared in software bus collision occurs. set bclif. scl = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sda scl sen set s less than t brg t brg sda = 0 , scl = 1 bclif s sspif s interrupts cleared in software set sspif sda = 0 , scl = 1 , scl pulled low after brg time-out set sspif ? 0 ? sda pulled low by other master. reset brg and assert sda. set sen, enable start sequence if sda = 1 , scl = 1 pic18f85j11 family ds39774c-page 214 preliminary ? 2007 microchip technology inc. 16.4.17.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indicating that another master is attempting to transmit a data ? 1 ?. when the user deasserts sda and the pin is allowed to float high, the brg is loaded with sspadd<6:0> and counts down to 0. the scl pin is then deasserted and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ?, see figure 16-31). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high-to-low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high-to-low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condition (see figure 16-32). if, at the end of the brg time-out, both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 16-31: bus collision during a repeat ed start condition (case 1) figure 16-32: bus collision during repeat ed start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0 , set bclif and release sda and scl. cleared in software ? 0 ? ? 0 ? sda scl bclif rsen s sspif interrupt cleared in software scl goes low before sda, set bclif. release sda and scl. t brg t brg ? 0 ? ? 2007 microchip technology inc. preliminary ds39774c-page 215 pic18f85j11 family 16.4.17.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been deasserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is deasserted, scl is sampled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd<6:0> and counts down to 0. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? (figure 16-33). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data ? 0 ? (figure 16-34). figure 16-33: bus collision during a stop condition (case 1) figure 16-34: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif ? 0 ? ? 0 ? sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high, set bclif ? 0 ? ? 0 ? pic18f85j11 family ds39774c-page 216 preliminary ? 2007 microchip technology inc. table 16-4: registers associated with i 2 c? operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir1 pspif adif rc1if tx1if sspif ? tmr2if tmr1if 53 pie1 pspie adie rc1ie tx1ie sspie ? tmr2ie tmr1ie 53 ipr1 pspip adip rc1ip tx1ip sspip ? tmr2ip tmr1ip 53 pir2 oscfif cmif ? ?bclif lvdif tmr3if ?53 pie2 oscfie cmie ? ?bclie lvdie tmr3ie ?53 ipr2 oscfip cmip ? ?bclip lvdip tmr3ip ?53 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 54 sspbuf mssp receive buffer/transmit register 52 sspadd mssp address register (i 2 c? slave mode), mssp baud rate reload register (i 2 c master mode) 52 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 52 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 52 gcen ackstat admsk5 (1) admsk4 (1) admsk3 (1) admsk2 (1) admsk1 (1) sen sspstat smp cke d/a psr/w ua bf 52 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the mssp module in i 2 c? mode. note 1: alternate bit definitions for use in i 2 c slave mode operations only. ? 2007 microchip technology inc. preliminary ds39774c-page 217 pic18f85j11 family 17.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) pic18f85j11 family devices have three serial i/o modules: the mssp module, discussed in the previous chapter and two universal synchronous asynchronous receiver transmitter (usart) modules. (generically, the usart is also known as a serial communications interface or sci.) the eusart can be configured as a full-duplex, asynchronous system that can communicate with peripheral devices, such as crt terminals and per- sonal computers. it can also be configured as a half-duplex, synchronous system that can communicate with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms, etc. there are two distinct implementations of the usart module in these devices: the enhanced usart (eusart) discussed here and the addressable usart discussed in the next chapter. for this device family, usart1 always refers to the eusart, while usart2 is always the ausart. the eusart and ausart modules implement the same core features for serial communications; their basic operation is essentially the same. the eusart module provides additional features, including auto- matic baud rate detection and calibration, automatic wake-up on sync break reception and 12-bit break character transmit. these features make it ideally suited for use in local interconnect network bus (lin bus) systems. the eusart can be configured in the following modes: ? asynchronous (full-duplex) with: - auto-wake-up on character reception - auto-baud calibration - 12-bit break character transmission ? synchronous ? master (half-duplex) with selectable clock polarity ? synchronous ? slave (half-duplex) with selectable clock polarity the pins of the eusart are multiplexed with the functions of portc (rc6/tx1/ck1 and rc7/rx1/dt1). in order to configure these pins as a eusart: ? bit spen (rcsta1<7>) must be set (= 1 ) ? bit trisc<7> must be set (= 1 ) ? bit trisc<6> must be set (= 1 ) the driver for the tx1 output pin can also be optionally configured as an open-drain output. this feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor, and allows the output to communicate with external circuits without the need for additional level shifters. the open-drain output option is controlled by the u1od bit (latg<6>). setting the bit configures the pin for open-drain operation. 17.1 control registers the operation of the enhanced usart module is controlled through three registers: ? transmit status and control register 1 (txsta1) ? receive status and control register 1 (rcsta1) ? baud rate control register 1 (baudcon1) the registers are described in register 17-1, register 17-2 and register 17-3. note: the eusart control will automatically reconfigure the pin from input to output as needed. pic18f85j11 family ds39774c-page 218 preliminary ? 2007 microchip technology inc. register 17-1: txsta1: eusart transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-1 r/w-0 csrc tx9 txen (1) sync sendb brgh trmt tx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 csrc: clock source select bit asynchronous mode: don?t care. synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit enabled 0 = transmit disabled bit 4 sync: ausart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 sendb: send break character bit asynchronous mode: 1 = send sync break on next transmission (cleared by hardware upon completion) 0 = sync break transmission completed synchronous mode: don?t care. bit 2 brgh: high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode. bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data can be address/data bit or a parity bit. note 1: sren/cren overrides txen in sync mode. ? 2007 microchip technology inc. preliminary ds39774c-page 219 pic18f85j11 family register 17-2: rcsta1: eusart receive status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx1/dt1 and tx1/ck1 pins as serial port pins) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : don?t care. synchronous mode ? master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? slave: don?t care. bit 4 cren: continuous receive enable bit asynchronous mode: 1 = enables receiver 0 = disables receiver synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ) : 1 = enables address detection, enables interrupt and loads the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 9-bit (rx9 = 0 ) : don?t care. bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcreg1 register and receiving next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data this can be address/data bit or a parity bit and must be calculated by user firmware. pic18f85j11 family ds39774c-page 220 preliminary ? 2007 microchip technology inc. register 17-3: baudcon1: baud rate control register 1 r/w-0 r-1 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 abdovf rcmt ? sckp brg16 ? wue abden bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 abdovf : auto-baud acquisition rollover status bit 1 = a brg rollover has occurred during auto-baud rate detect mode (must be cleared in software) 0 = no brg rollover has occurred bit 6 rcmt : receive operation idle status bit 1 = receive operation is idle 0 = receive operation is active bit 5 unimplemented: read as ? 0 ? bit 4 sckp : synchronous clock polarity select bit asynchronous mode: unused in this mode. synchronous mode: 1 = idle state for clock (ck1) is a high level 0 = idle state for clock (ck1) is a low level bit 3 brg16: 16-bit baud rate register enable bit 1 = 16-bit baud rate generator ? spbrgh1 and spbrg1 0 = 8-bit baud rate generator ? spbrg1 only (compatible mode), spbrgh1 value ignored bit 2 unimplemented: read as ? 0 ? bit 1 wue: wake-up enable bit asynchronous mode: 1 = eusart will continue to sample the rx1 pin ? interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = rx1 pin not monitored or rising edge detected synchronous mode: unused in this mode. bit 0 abden : auto-baud detect enable bit asynchronous mode: 1 = enable baud rate measurement on the next character. requires reception of a sync field (55h); cleared in hardware upon completion. 0 = baud rate measurement disabled or completed synchronous mode: unused in this mode. ? 2007 microchip technology inc. preliminary ds39774c-page 221 pic18f85j11 family 17.2 eusart baud rate generator (brg) the brg is a dedicated, 8-bit or 16-bit generator that supports both the asynchronous and synchronous modes of the eusart. by default, the brg operates in 8-bit mode; setting the brg16 bit (baudcon1<3>) selects 16-bit mode. the spbrgh1:spbrg1 register pair controls the period of a free-running timer. in asynchronous mode, brgh (txsta1<2>) and brg16 (baudcon1<3>) bits also control the baud rate. in synchronous mode, brgh is ignored. table 17-1 shows the formula for computa- tion of the baud rate for different eusart modes that only apply in master mode (internally generated clock). given the desired baud rate and f osc , the nearest integer value for the spbrgh1:spbrg1 registers can be calculated using the formulas in table 17-1. from this, the error in baud rate can be determined. an example calculation is shown in example 17-1. typical baud rates and error values for the various asynchronous modes are shown in table 17-2. it may be advantageous to use the high baud rate (brgh = 1 ) or the 16-bit brg to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. writing a new value to the spbrgh1:spbrg1 regis- ters causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before outputting the new baud rate. 17.2.1 operation in power-managed modes the device clock is used to generate the desired baud rate. when one of the power-managed modes is entered, the new clock source may be operating at a different frequency. this may require an adjustment to the value in the spbrg1 register pair. 17.2.2 sampling the data on the rx1 pin is sampled three times by a majority detect circuit to determine if a high or low level is present at the rx1 pin. table 17-1: baud rate formulas example 17-1: calculating baud rate error table 17-2: registers associated with the baud rate generator configuration bits brg/eusart mode baud rate formula sync brg16 brgh 000 8-bit/asynchronous f osc /[64 (n + 1)] 001 8-bit/asynchronous f osc /[16 (n + 1)] 010 16-bit/asynchronous 011 16-bit/asynchronous f osc /[4 (n + 1)] 10x 8-bit/synchronous 11x 16-bit/synchronous legend: x = don?t care, n = value of spbrgh1:spbrg1 register pair name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 53 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 53 baudcon1 abdovf rcmt ? sckp brg16 ? wue abden 54 spbrgh1 eusart baud rate generator register high byte 54 spbrg1 eusart baud rate generator register low byte 53 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the brg. for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, 8-bit brg: desired baud rate = f osc /(64 ([spbrgh1:spbrg1] + 1)) solving for spbrgh1:spbrg1: x=((f osc /desired baud rate)/64) ? 1 = ((16000000/9600)/64) ? 1 = [25.042] = 25 calculated baud rate = 16000000/(64 (25 + 1)) = 9615 error = (calculated baud rate ? desi red baud rate)/de sired baud rate = (9615 ? 9600)/9600 = 0.16% pic18f85j11 family ds39774c-page 222 preliminary ? 2007 microchip technology inc. table 17-3: baud rates for asynchronous modes baud rate (k) sync = 0 , brgh = 0 , brg16 = 0 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3???????????? 1.2 ? ? ? 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 ? ? ? 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 ? ? ? 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 ? ? ? baud rate (k) sync = 0 , brgh = 0 , brg16 = 0 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.404 0.16 25 2.403 -0.16 12 ? ? ? 9.6 8.929 -6.99 6 ? ? ? ? ? ? 19.2 20.833 8.51 2 ? ? ? ? ? ? 57.6 62.500 8.51 0 ? ? ? ? ? ? 115.2 62.500 -45.75 0 ? ? ? ? ? ? baud rate (k) sync = 0 , brgh = 1 , brg16 = 0 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3???????????? 1.2???????????? 2.4 ? ? ? ? ? ? 2.441 1.73 255 2.403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 ? ? ? baud rate (k) sync = 0 , brgh = 1 , brg16 = 0 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 ? ? ? ? ? ? 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 ? ? ? 19.2 19.231 0.16 12 ? ? ? ? ? ? 57.6 62.500 8.51 3 ? ? ? ? ? ? 115.2 125.000 8.51 1 ? ? ? ? ? ? ? 2007 microchip technology inc. preliminary ds39774c-page 223 pic18f85j11 family baud rate (k) sync = 0 , brgh = 0 , brg16 = 1 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 ? ? ? baud rate (k) sync = 0 , brgh = 0 , brg16 = 1 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 ? ? ? 19.2 19.231 0.16 12 ? ? ? ? ? ? 57.6 62.500 8.51 3 ? ? ? ? ? ? 115.2 125.000 8.51 1 ? ? ? ? ? ? baud rate (k) sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16 baud rate (k) sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832 1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207 2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103 9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25 19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12 57.6 58.824 2.12 16 55.555 3.55 8 ? ? ? 115.2 111.111 -3.55 8 ? ? ? ? ? ? table 17-3: baud rates for asynchronous modes (continued) pic18f85j11 family ds39774c-page 224 preliminary ? 2007 microchip technology inc. 17.2.3 auto-baud rate detect the enhanced usart module supports the automatic detection and calibration of baud rate. this feature is active only in asynchronous mode and while the wue bit is clear. the automatic baud rate measurement sequence (figure 17-1) begins whenever a start bit is received and the abden bit is set. the calculation is self-averaging. in the auto-baud rate detect (abd) mode, the clock to the brg is reversed. rather than the brg clocking the incoming rx1 signal, the rx1 signal is timing the brg. in abd mode, the internal baud rate generator is used as a counter to time the bit period of the incoming serial byte stream. once the abden bit is set, the state machine will clear the brg and look for a start bit. the auto-baud rate detect must receive a byte with the value, 55h (ascii ?u?, which is also the lin bus sync character), in order to calculate the proper bit rate. the measurement is taken over both a low and high bit time in order to min- imize any effects caused by asymmetry of the incoming signal. after a start bit, the spbrg1 begins counting up, using the preselected clock source on the first rising edge of rx1. after eight bits on the rx1 pin, or the fifth rising edge, an accumulated value totalling the proper brg period is left in the spbrgh1:spbrg1 register pair. once the 5th edge is seen (this should correspond to the stop bit), the abden bit is automatically cleared. if a rollover of the brg occurs (an overflow from ffffh to 0000h), the event is trapped by the abdovf status bit (baudcon1<7>). it is set in hardware by brg rollovers and can be set or cleared by the user in software. abd mode remains active after rollover events and the abden bit remains set (figure 17-2). while calibrating the baud rate period, the brg regis- ters are clocked at 1/8th the preconfigured clock rate. note that the brg clock will be configured by the brg16 and brgh bits. independent of the brg16 bit setting, both the spbrg1 and spbrgh1 will be used as a 16-bit counter. this allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the spbrgh1 register. refer to table 17-4 for counter clock rates to the brg. while the abd sequence takes place, the eusart state machine is held in idle. the rc1if interrupt is set once the fifth rising edge on rx1 is detected. the value in the rcreg1 needs to be read to clear the rc1if interrupt. the contents of rcreg1 should be discarded. table 17-4: brg counter clock rates 17.2.3.1 abd and eusart transmission since the brg clock is reversed during abd acquisi- tion, the eusart transmitter cannot be used during abd. this means that whenever the abden bit is set, txreg1 cannot be written to. users should also ensure that abden does not become set during a transmit sequence. failing to do this may result in unpredictable eusart operation. note 1: if the wue bit is set with the abden bit, auto-baud rate detection will occur on the byte following the break character. 2: it is up to the user to determine that the incoming character baud rate is within the range of the selected brg clock source. some combinations of oscillator frequency and eusart baud rates are not possible due to bit error rates. overall system timing and communication baud rates must be taken into consideration when using the auto-baud rate detection feature. brg16 brgh brg counter clock 00 f osc /512 01 f osc /128 10 f osc /128 11 f osc /32 note: during the abd sequence, spbrg1 and spbrgh1 are both used as a 16-bit counter, independent of the brg16 setting. ? 2007 microchip technology inc. preliminary ds39774c-page 225 pic18f85j11 family figure 17-1: automatic baud rate calculation figure 17-2: brg overflow sequence brg value rx1 pin abden bit rc1if bit bit 0 bit 1 (interrupt) read rcreg1 brg clock start auto-cleared set by user xxxxh 0000h edge #1 bit 2 bit 3 edge #2 bit 4 bit 5 edge #3 bit 6 bit 7 edge #4 001ch note: the abd sequence requires the eusart module to be configured in asynchronous mode and wue = 0 . spbrg1 xxxxh 1ch spbrgh1 xxxxh 00h stop bit edge #5 start bit 0 xxxxh 0000h 0000h ffffh brg clock abden bit rx1 pin abdovf bit brg value pic18f85j11 family ds39774c-page 226 preliminary ? 2007 microchip technology inc. 17.3 eusart asynchronous mode the asynchronous mode of operation is selected by clearing the sync bit (txsta1<4>). in this mode, the eusart uses standard non-return-to-zero (nrz) for- mat (one start bit, eight or nine data bits and one stop bit). the most common data format is 8 bits. an on-chip, dedicated 8-bit/16-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the eusart transmits and receives the lsb first. the eusart?s transmitter and receiver are functionally independent, but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on the brgh and brg16 bits (txsta1<2> and baudcon1<3>). parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit. when operating in asynchronous mode, the eusart module consists of the following important elements: ? baud rate generator ? sampling circuit ? asynchronous transmitter ? asynchronous receiver ? auto-wake-up on sync break character ? 12-bit break character transmit ? auto-baud rate detection 17.3.1 eusart asynchronous transmitter the eusart transmitter block diagram is shown in figure 17-3. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg1. the txreg1 register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg1 register (if available). once the txreg1 register transfers the data to the tsr register (occurs in one t cy ), the txreg1 register is empty and the tx1if flag bit (pir1<4>) is set. this inter- rupt can be enabled or disabled by setting or clearing the interrupt enable bit, tx1ie (pie1<4>). tx1if will be set regardless of the state of tx 1ie; it cannot be cleared in software. tx1if is also not cleared immediately upon loading txreg1, but becomes valid in the second instruction cycle following the load instruction. polling tx1if immediately following a load of txreg1 will return invalid results. while tx1if indicates the status of the txreg1 regis- ter, another bit, trmt (txsta1<1>), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr register is empty. no interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the tsr register is empty. to set up an asynchronous transmission: 1. initialize the spbrgh1:spbrg1 registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit, sync, and setting bit, spen. 3. if interrupts are desired, set enable bit, tx1ie. 4. if 9-bit transmission is desired, set transmit bit, tx9; can be used as address/data bit. 5. enable the transmission by setting bit, txen, which will also set bit, tx1if. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit, tx9d. 7. load data to the txreg1 register (starts transmission). 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 17-3: eusart transmit block diagram note 1: the tsr register is not mapped in data memory so it is not available to the user. 2: flag bit, tx1if, is set when enable bit, txen, is set. tx1if tx1ie interrupt txen baud rate clk spbrg1 baud rate generator tx9d msb lsb data bus txreg1 register tsr register (8) 0 tx9 trmt spen tx1 pin pin buffer and control 8 ? ? ? spbrgh1 brg16 ? 2007 microchip technology inc. preliminary ds39774c-page 227 pic18f85j11 family figure 17-4: asynchronous transmission figure 17-5: asynchronous transmiss ion (back-to-back) table 17-5: registers associated with asynchronous transmission word 1 word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg1 brg output (shift clock) tx1 (pin) tx1if bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy word 1 stop bit transmit shift reg. write to txreg1 brg output (shift clock) tx1 (pin) tx1if bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy start bit name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir1 pspif adif rc1if tx1if sspif ? tmr2if tmr1if 53 pie1 pspie adie rc1ie tx1ie sspie ? tmr2ie tmr1ie 53 ipr1 pspip adip rc1ip tx1ip sspip ? tmr2ip tmr1ip 53 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 53 txreg1 eusart transmit register 53 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 53 baudcon1 abdovf rcmt ? sckp brg16 ? wue abden 54 spbrgh1 eusart baud rate generator register high byte 54 spbrg1 eusart baud rate generator register low byte 53 latg u2od u1od ? latg4 latg3 latg2 latg1 latg0 54 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous transmission. pic18f85j11 family ds39774c-page 228 preliminary ? 2007 microchip technology inc. 17.3.2 eusart asynchronous receiver the receiver block diagram is shown in figure 17-6. the data is received on the rx1 pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . this mode would typically be used in rs-232 systems. to set up an asynchronous reception: 1. initialize the spbrgh1:spbrg1 registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit, sync, and setting bit, spen. 3. if interrupts are desired, set enable bit, rc1ie. 4. if 9-bit reception is desired, set bit, rx9. 5. enable the reception by setting bit, cren. 6. flag bit, rc1if, will be set when reception is complete and an interrupt will be generated if enable bit, rc1ie, was set. 7. read the rcsta1 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg1 register. 9. if any error occurred, clear the error by clearing enable bit, cren. 10. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. 17.3.3 setting up 9-bit mode with address detect this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrgh1:spbrg1 registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are required, set the rcen bit and select the desired priority level with the rc1ip bit. 4. set the rx9 bit to enable 9-bit reception. 5. set the adden bit to enable address detect. 6. enable reception by setting the cren bit. 7. the rc1if bit will be set when reception is complete. the interrupt will be acknowledged if the rc1ie and gie bits are set. 8. read the rcsta1 register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. read rcreg1 to determine if the device is being addressed. 10. if any error occurred, clear the cren bit. 11. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and interrupt the cpu. figure 17-6: eusart receiv e block diagram x64 baud rate clk baud rate generator rx1 pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg1 register fifo interrupt rc1if rc1ie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? spbrg1 spbrgh1 brg16 or 4 ? 2007 microchip technology inc. preliminary ds39774c-page 229 pic18f85j11 family figure 17-7: asynchronous reception table 17-6: registers associated with asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx1 (pin) rcv buffer reg rcv shift reg read rcv buffer reg rcreg1 rc1if (interrupt flag) oerr bit cren bit word 1 rcreg1 word 2 rcreg1 stop bit note: this timing diagram shows three words appearing on the rx1 input. the rcreg1 (eusart receive register) is read after the third word causing the oerr (overrun error) bit to be set. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir1 pspif adif rc1if tx1if sspif ? tmr2if tmr1if 53 pie1 pspie adie rc1ie tx1ie sspie ? tmr2ie tmr1ie 53 ipr1 pspip adip rc1ip tx1ip sspip ? tmr2ip tmr1ip 53 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 53 rcreg1 eusart receive register 53 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 53 baudcon1 abdovf rcmt ? sckp brg16 ? wue abden 54 spbrgh1 eusart baud rate generator register high byte 54 spbrg1 eusart baud rate generator register low byte 53 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception. pic18f85j11 family ds39774c-page 230 preliminary ? 2007 microchip technology inc. 17.3.4 auto-wake-up on sync break character during sleep mode, all clocks to the eusart are suspended. because of this, the baud rate generator is inactive and a proper byte reception cannot be per- formed. the auto-wake-up feature allows the controller to wake-up due to activity on the rx1/dt1 line, while the eusart is operating in asynchronous mode. the auto-wake-up feature is enabled by setting the wue bit (baudcon<1>). once set, the typical receive sequence on rx1/dt1 is disabled and the eusart remains in an idle state, monitoring for a wake-up event independent of the cpu mode. a wake-up event consists of a high-to-low transition on the rx1/dt1 line. (this coincides with the start of a sync break or a wake-up signal character for the lin protocol.) following a wake-up event, the module generates an rc1if interrupt. the interrupt is generated synchro- nously to the q clocks in normal operating modes (figure 17-8), and asynchronously, if the device is in sleep mode (figure 17-9). the interrupt condition is cleared by reading the rcreg1 register. the wue bit is automatically cleared once a low-to-high transition is observed on the rx1 line following the wake-up event. at this point, the eusart module is in idle mode and returns to normal operation. this signals to the user that the sync break event is over. 17.3.4.1 special considerations using auto-wake-up since auto-wake-up functions by sensing rising edge transitions on rx1/dt1, information with any state changes before the stop bit may signal a false end-of-character (eoc) and cause data or framing errors. therefore, to work properly, the initial character in the transmission must be all ? 0 ?s. this can be 00h (8 bytes) for standard rs-232 devices or 000h (12 bits) for lin bus. oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., xt or hs mode). the sync break (or wake-up signal) character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the eusart. 17.3.4.2 special considerations using the wue bit the timing of wue and rc1if events may cause some confusion when it comes to determining the validity of received data. as noted, setting the wue bit places the eusart in an idle mode. the wake-up event causes a receive interrupt by setting the rc1if bit. the wue bit is cleared after this when a rising edge is seen on rx1/dt1. the interrupt condition is then cleared by reading the rcreg1 register. ordinarily, the data in rcreg1 will be dummy data and should be discarded. the fact that the wue bit has been cleared (or is still set) and the rc1if flag is set should not be used as an indicator of the integrity of the data in rcreg1. users should consider implementing a parallel method in firmware to verify received data integrity. to assure that no actual data is lost, check the rcmt bit to verify that a receive operation is not in process. if a receive operation is not occurring, the wue bit may then be set just prior to entering the sleep mode. figure 17-8: auto-wake-up bit (wue) timings during normal operation figure 17-9: auto-wake-up bit (wue) timings during sleep q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit (1) rx1/dt1 line rc1if cleared due to user read of rcreg1 note 1: the eusart remains in idle while the wue bit is set. bit set by user auto-cleared q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit (2) rx1/dt1 line rc1if cleared due to user read of rcreg1 sleep command executed note 1: if the wake-up event requires long oscillator warm-up time, the auto-clear of the wue bit can occur while the stposc signal is still active. this sequence should not depend on the presence of q clocks. 2: the eusart remains in idle while the wue bit is set. sleep ends auto-cleared note 1 bit set by user ? 2007 microchip technology inc. preliminary ds39774c-page 231 pic18f85j11 family 17.3.5 break character sequence the enhanced usart module has the capability of sending the special break character sequences that are required by the lin bus standard. the break char- acter transmit consists of a start bit, followed by twelve ? 0 ? bits and a stop bit. the frame break character is sent whenever the sendb and txen bits (txsta1<3> and txsta1<5>) are set while the trans- mit shift register is loaded with data. note that the value of data written to txreg1 will be ignored and all ? 0 ?s will be transmitted. the sendb bit is automatically reset by hardware after the corresponding stop bit is sent. this allows the user to preload the transmit fifo with the next transmit byte following the break character (typically, the sync char- acter in the lin specification). note that the data value written to the txreg1 for the break character is ignored. the write simply serves the purpose of initiating the proper sequence. the trmt bit indicates when the transmit operation is active or idle, just as it does during normal transmis- sion. see figure 17-10 for the timing of the break character sequence. 17.3.5.1 break and sync transmit sequence the following sequence will send a message frame header made up of a break, followed by an auto-baud sync byte. this sequence is typical of a lin bus master. 1. configure the eusart for the desired mode. 2. set the txen and sendb bits to set up the break character. 3. load the txreg1 with a dummy character to initiate transmission (the value is ignored). 4. write ?55h? to txreg1 to load the sync character into the transmit fifo buffer. 5. after the break has been sent, the sendb bit is reset by hardware. the sync character now transmits in the preconfigured mode. when the txreg1 becomes empty, as indicated by the tx1if, the next data byte can be written to txreg1. 17.3.6 receiving a break character the enhanced usart module can receive a break character in two ways. the first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. this allows for the stop bit transition to be at the correct sampling location (13 bits for break versus start bit and 8 data bits for typical data). the second method uses the auto-wake-up feature described in section 17.3.4 ?auto-wake-up on sync break character? . by enabling this feature, the eusart will sample the next two transitions on rx1/dt1, cause an rc1if interrupt and receive the next data byte followed by another interrupt. note that following a break character, the user will typically want to enable the auto-baud rate detect feature. for both methods, the user can set the abden bit once the tx1if interrupt is observed. figure 17-10: send break character sequence write to txreg1 brg output (shift clock) start bit bit 0 bit 1 bit 11 stop bit break tx1if bit (transmit buffer reg. empty flag) tx1 (pin) trmt bit (transmit shift reg. empty flag) sendb (transmit shift reg. empty flag) sendb sampled here auto-cleared dummy write pic18f85j11 family ds39774c-page 232 preliminary ? 2007 microchip technology inc. 17.4 eusart synchronous master mode the synchronous master mode is entered by setting the csrc bit (txsta1<7>). in this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit, sync (txsta1<4>). in addition, enable bit, spen (rcsta1<7>), is set in order to configure the tx1 and rx1 pins to ck1 (clock) and dt1 (data) lines, respectively. the master mode indicates that the processor trans- mits the master clock on the ck1 line. clock polarity is selected with the sckp bit (baudcon1<4>). setting sckp sets the idle state on ck1 as high, while clearing the bit sets the idle state as low. this option is provided to support microwire devices with this module. 17.4.1 eusart synchronous master transmission the eusart transmitter block diagram is shown in figure 17-3. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg1. the txreg1 register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg1 (if available). once the txreg1 register transfers the data to the tsr register (occurs in one t cycle ), the txreg1 is empty and the tx1if flag bit (pir1<4>) is set. the interrupt can be enabled or disabled by setting or clear- ing the interrupt enable bit, tx1ie (pie1<4>). tx1if is set regardless of the state of enable bit, tx1ie; it can- not be cleared in software. it will reset only when new data is loaded into the txreg1 register. while flag bit tx1if indicates the status of the txreg1 register, another bit, trmt (txsta1<1>), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr is empty. no interrupt logic is tied to this bit so the user has to poll this bit in order to deter- mine if the tsr register is empty. the tsr is not mapped in data memory so it is not available to the user. to set up a synchronous master transmission: 1. initialize the spbrgh1:spbrg1 registers for the appropriate baud rate. set or clear the brg16 bit, as required, to achieve the desired baud rate. 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if interrupts are desired, set enable bit, tx1ie. 4. if 9-bit transmission is desired, set bit, tx9. 5. enable the transmission by setting bit, txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg1 register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 17-11: synchronous transmission bit 0 bit 1 bit 7 word 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx1/dt1 rc6/tx1/ck1 pin write to txreg1 reg tx1if bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrg1 = 0 ; continuous transmission of two 8-bit words. pin rc6/tx1/ck1 pin (sckp = 0 ) (sckp = 1 ) ? 2007 microchip technology inc. preliminary ds39774c-page 233 pic18f85j11 family figure 17-12: synchronous transmis sion (through txen) table 17-7: registers associated with synchronous master transmission rc7/rx1/dt1 pin rc6/tx1/ck1 pin write to txreg1 reg tx1if bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir1 pspif adif rc1if tx1if sspif ? tmr2if tmr1if 53 pie1 pspie adie rc1ie tx1ie sspie ? tmr2ie tmr1ie 53 ipr1 pspip adip rc1ip tx1ip sspip ? tmr2ip tmr1ip 53 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 53 txreg1 eusart transmit register 53 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 53 baudcon1 abdovf rcmt ?sckpbrg16 ? wue abden 54 spbrgh1 eusart baud rate generator register high byte 54 spbrg1 eusart baud rate generator register low byte 53 latg u2od u1od ? latg4 latg3 latg2 latg1 latg0 54 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master transmission. pic18f85j11 family ds39774c-page 234 preliminary ? 2007 microchip technology inc. 17.4.2 eusart synchronous master reception once synchronous mode is selected, reception is enabled by setting either the single receive enable bit, sren (rcsta1<5>), or the continuous receive enable bit, cren (rcsta1<4>). data is sampled on the rx1 pin on the falling edge of the clock. if enable bit, sren, is set, only a single word is received. if enable bit, cren, is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. to set up a synchronous master reception: 1. initialize the spbrgh1:spbrg1 registers for the appropriate baud rate. set or clear the brg16 bit, as required, to achieve the desired baud rate. 2. enable the synchronous master serial port by setting bits, sync, spen and csrc. 3. ensure bits, cren and sren, are clear. 4. if interrupts are desired, set enable bit, rc1ie. 5. if 9-bit reception is desired, set bit, rx9. 6. if a single reception is required, set bit, sren. for continuous reception, set bit, cren. 7. interrupt flag bit, rc1if, will be set when reception is complete and an interrupt will be generated if the enable bit, rc1ie, was set. 8. read the rcsta1 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg1 register. 10. if any error occurred, clear the error by clearing bit, cren. 11. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 17-13: synchronous reception (master mode, sren) table 17-8: registers associated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir1 pspif adif rc1if tx1if sspif ? tmr2if tmr1if 53 pie1 pspie adie rc1ie tx1ie sspie ? tmr2ie tmr1ie 53 ipr1 pspip adip rc1ip tx1ip sspip ? tmr2ip tmr1ip 53 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 53 rcreg1 eusart receive register 53 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 53 baudcon1 abdovf rcmt ? sckp brg16 ? wue abden 54 spbrgh1 eusart baud rate generator register high byte 54 spbrg1 eusart baud rate generator register low byte 53 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master reception. cren bit rc7/rx1/dt1 rc6/tx1/ck1 pin write to sren bit sren bit rc1if bit (interrupt) read rcreg1 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? q1 q2 q3 q4 note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . rc6/tx1/ck1 pin pin (sckp = 0 ) (sckp = 1 ) ? 2007 microchip technology inc. preliminary ds39774c-page 235 pic18f85j11 family 17.5 eusart synchronous slave mode synchronous slave mode is entered by clearing bit, csrc (txsta<7>). this mode differs from the synchronous master mode in that the shift clock is sup- plied externally at the ck1 pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in any low-power mode. 17.5.1 eusart synchronous slave transmit the operation of the synchronous master and slave modes are identical except in the case of the sleep mode. if two words are written to the txreg1 and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in the txreg1 register. c) flag bit, tx1if, will not be set. d) when the first word has been shifted out of tsr, the txreg1 register will transfer the second word to the tsr and flag bit, tx1if, will now be set. e) if enable bit, tx1ie, is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave transmission: 1. enable the synchronous slave serial port by setting bits, sync and spen, and clearing bit, csrc. 2. clear bits, cren and sren. 3. if interrupts are desired, set enable bit, tx1ie. 4. if 9-bit transmission is desired, set bit, tx9. 5. enable the transmission by setting enable bit, txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg1 register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 17-9: registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir1 pspif adif rc1if tx1if sspif ? tmr2if tmr1if 53 pie1 pspie adie rc1ie tx1ie sspie ? tmr2ie tmr1ie 53 ipr1 pspip adip rc1ip tx1ip sspip ? tmr2ip tmr1ip 53 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 53 txreg1 eusart transmit register 53 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 53 baudcon1 abdovf rcmt ? sckp brg16 ? wue abden 54 spbrgh1 eusart baud rate generator register high byte 54 spbrg1 eusart baud rate generator register low byte 53 latg u2od u1od ? latg4 latg3 latg2 latg1 latg0 54 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave transmission. pic18f85j11 family ds39774c-page 236 preliminary ? 2007 microchip technology inc. 17.5.2 eusart synchronous slave reception the operation of the synchronous master and slave modes is identical except in the case of sleep or any idle mode, and bit sren, which is a ?don?t care? in slave mode. if receive is enabled by setting the cren bit prior to entering sleep or any idle mode, then a word may be received while in this low-power mode. once the word is received, the rsr register will transfer the data to the rcreg1 register. if the rc1ie enable bit is set, the interrupt generated will wake the chip from the low-power mode. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits, sync and spen, and clearing bit, csrc. 2. if interrupts are desired, set enable bit, rc1ie. 3. if 9-bit reception is desired, set bit, rx9. 4. to enable reception, set enable bit, cren. 5. flag bit, rc1if, will be set when reception is complete. an interrupt will be generated if enable bit, rc1ie, was set. 6. read the rcsta1 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg1 register. 8. if any error occurred, clear the error by clearing bit, cren. 9. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 17-10: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir1 pspif adif rc1if tx1if sspif ? tmr2if tmr1if 53 pie1 pspie adie rc1ie tx1ie sspie ? tmr2ie tmr1ie 53 ipr1 pspip adip rc1ip tx1ip sspip ? tmr2ip tmr1ip 53 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 53 rcreg1 eusart receive register 53 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 53 baudcon1 abdovf rcmt ?sckpbrg16 ? wue abden 54 spbrgh1 eusart baud rate generator register high byte 54 spbrg1 eusart baud rate generator register low byte 53 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave reception. ? 2007 microchip technology inc. preliminary ds39774c-page 237 pic18f85j11 family 18.0 addressable universal synchronous asynchronous receiver transmitter (ausart) the addressable universal synchronous asynchro- nous receiver transmitter (ausart) module is very similar in function to the enhanced usart module discussed in the previous chapter. it is provided as an additional channel for serial communication with external devices for those situations that do not require auto-baud detection or lin bus support. the ausart can be configured in the following modes: ? asynchronous (full-duplex) ? synchronous ? master (half-duplex) ? synchronous ? slave (half-duplex) the pins of the ausart module are multiplexed with the functions of portg (rg1/tx2/ck2 and rg2/rx2/dt2, respectively). in order to configure these pins as an ausart: ? bit spen (rcsta2<7>) must be set (= 1 ) ? bit trisg<2> must be set (= 1 ) ? bit trisg<1> must be cleared (= 0 ) for asynchronous and synchronous master modes ? bit trisg<1> must be set (= 1 ) for synchronous slave mode the driver for the tx2 output pin can also be optionally configured as an open-drain output. this feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor, and allows the output to communicate with external circuits without the need for additional level shifters. the open-drain output option is controlled by the u2od bit (latg<7>). setting this bit configures the pin for open-drain operation. 18.1 control registers the operation of the addressable usart module is controlled through two registers, txsta2 and rcsta2. these are detailed in register 18-1 and register 18-2, respectively. note: the ausart control will automatically reconfigure the pin from input to output as needed. pic18f85j11 family ds39774c-page 238 preliminary ? 2007 microchip technology inc. register 18-1: txsta2: ausart transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen (1) sync ? brgh trmt tx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 csrc: clock source select bit asynchronous mode: don?t care. synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit enabled 0 = transmit disabled bit 4 sync: ausart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as ? 0 ? bit 2 brgh: high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode. bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data can be address/data bit or parity bit. note 1: sren/cren overrides txen in sync mode. ? 2007 microchip technology inc. preliminary ds39774c-page 239 pic18f85j11 family register 18-2: rcsta2: ausart receive stat us and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx2/dt2 and tx2/ck2 pins as serial port pins) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : don?t care. synchronous mode ? master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? slave: don?t care. bit 4 cren: continuous receive enable bit asynchronous mode: 1 = enables receiver 0 = disables receiver synchronous mode: 1 = enables continuous receive until enable bit, cren, is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9- bit (rx9 = 1 ) : 1 = enables address detection, enables interrupt and loads the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 9- bit (rx9 = 0 ) : don?t care. bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcreg2 register and receiving next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing the cren bit) 0 = no overrun error bit 0 rx9d: 9th bit of received data this can be address/data bit or parity bit and must be calculated by user firmware. pic18f85j11 family ds39774c-page 240 preliminary ? 2007 microchip technology inc. 18.2 ausart baud rate generator (brg) the brg is a dedicated, 8-bit generator that supports both the asynchronous and synchronous modes of the ausart. the spbrg2 register controls the period of a free-running timer. in asynchronous mode, bit brgh (txsta<2>) also controls the baud rate. in synchro- nous mode, brgh is ignored. table 18-1 shows the formula for computation of the baud rate for different ausart modes, which only apply in master mode (internally generated clock). given the desired baud rate and f osc , the nearest integer value for the spbrg2 register can be calcu- lated using the formulas in table 18-1. from this, the error in baud rate can be determined. an example calculation is shown in example 18-1. typical baud rates and error values for the various asynchronous modes are shown in table 18-2. it may be advanta- geous to use the high baud rate (brgh = 1 ) to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. writing a new value to the spbrg2 register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before outputting the new baud rate. 18.2.1 operation in power-managed modes the device clock is used to generate the desired baud rate. when one of the power-managed modes is entered, the new clock source may be operating at a different frequency. this may require an adjustment to the value in the spbrg2 register. 18.2.2 sampling the data on the rx2 pin is sampled three times by a majority detect circuit to determine if a high or low level is present at the rx2 pin. table 18-1: baud rate formulas example 18-1: calculating baud rate error table 18-2: registers associated with the baud rate generator configuration bits brg/ausart mode baud rate formula sync brgh 00 asynchronous f osc /[64 (n + 1)] 01 asynchronous f osc /[16 (n + 1)] 1x synchronous f osc /[4 (n + 1)] legend: x = don?t care, n = value of spbrg2 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page txsta2 csrc tx9 txen sync ?brgh trmt tx9d 55 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 55 spbrg2 ausart baud rate generator register 55 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used by the brg. for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, brgh = 0 : desired baud rate = f osc /(64 ([spbrg2] + 1)) solving for spbrg2: x = ((f osc /desired baud rate)/64) ? 1 = ((16000000/9600)/64) ? 1 = [25.042] = 25 calculated baud rate = 16000000/(64 (25 + 1)) = 9615 error = (calculated baud rate ? desi red baud rate)/desired baud rate = (9615 ? 9600)/9600 = 0.16% ? 2007 microchip technology inc. preliminary ds39774c-page 241 pic18f85j11 family table 18-3: baud rates for asynchronous modes brgh = 0 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz baud rate (k) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3???????????? 1.2 ? ? ? 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 ? ? ? 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 ? ? ? 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 ? ? ? brgh = 0 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz baud rate (k) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.404 0.16 25 2.403 -0.16 12 ? ? ? 9.6 8.929 -6.99 6 ? ? ? ? ? ? 19.2 20.833 8.51 2 ? ? ? ? ? ? 57.6 62.500 8.51 0 ? ? ? ? ? ? 115.2 62.500 -45.75 0 ? ? ? ? ? ? baud rate (k) brgh = 1 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3???????????? 1.2???????????? 2.4 ? ? ? ? ? ? 2.441 1.73 255 2.403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 ? ? ? baud rate (k) brgh = 1 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 ? ? ? ? ? ? 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 ? ? ? 19.2 19.231 0.16 12 ? ? ? ? ? ? 57.6 62.500 8.51 3 ? ? ? ? ? ? 115.2 125.000 8.51 1 ? ? ? ? ? ? pic18f85j11 family ds39774c-page 242 preliminary ? 2007 microchip technology inc. 18.3 ausart asynchronous mode the asynchronous mode of operation is selected by clearing the sync bit (txsta2<4>). in this mode, the ausart uses standard non-return-to-zero (nrz) format (one start bit, eight or nine data bits and one stop bit). the most common data format is 8 bits. an on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the ausart transmits and receives the lsb first. the ausart?s transmitter and receiver are functionally independent but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on the brgh bit (txsta2<2>). parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit. when operating in asynchronous mode, the ausart module consists of the following important elements: ? baud rate generator ? sampling circuit ? asynchronous transmitter ? asynchronous receiver 18.3.1 ausart asynchronous transmitter the ausart transmitter block diagram is shown in figure 18-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg2. the txreg2 register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg2 register (if available). once the txreg2 register transfers the data to the tsr register (occurs in one t cy ), the txreg2 register is empty and the tx2if flag bit (pir3<4>) is set. this interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, tx2ie (pie3<4>). tx2if will be set regardless of the state of tx2ie; it cannot be cleared in software. tx2if is also not cleared immediately upon loading txreg2, but becomes valid in the second instruction cycle following the load instruction. polling tx2if immediately following a load of txreg2 will return invalid results. while tx2if indicates the status of the txreg2 register, another bit, trmt (txsta2<1>), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr register is empty. no inter- rupt logic is tied to this bit so the user has to poll this bit in order to determine if the tsr register is empty. to set up an asynchronous transmission: 1. initialize the spbrg2 register for the appropri- ate baud rate. set or clear the brgh bit, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are desired, set enable bit, tx2ie. 4. if 9-bit transmission is desired, set transmit bit, tx9; can be used as address/data bit. 5. enable the transmission by setting bit, txen, which will also set bit, tx2if. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit, tx9d. 7. load data to the txreg2 register (starts transmission). 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 18-1: ausart transmit block diagram note 1: the tsr register is not mapped in data memory so it is not available to the user. 2: flag bit, tx2if, is set when enable bit, txen, is set. tx2if tx2ie interrupt txen baud rate clk spbrg2 baud rate generator tx9d msb lsb data bus txreg2 register tsr register (8) 0 tx9 trmt spen tx2 pin pin buffer and control 8 ? ? ? ? 2007 microchip technology inc. preliminary ds39774c-page 243 pic18f85j11 family figure 18-2: asynchronous transmission figure 18-3: asynchronous transmiss ion (back-to-back) table 18-4: registers associated with asynchronous transmission word 1 word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg2 brg output (shift clock) tx2 (pin) tx2if bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy word 1 stop bit transmit shift reg. write to txreg2 brg output (shift clock) tx2 (pin) tx2if bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy start bit name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir3 ? ? rc2if tx2if ? ccp2if ccp1if ?53 pie3 ? ? rc2ie tx2ie ? ccp2ie ccp1ie ?53 ipr3 ? ? rc2ip tx2ip ? ccp2ip ccp1ip ?53 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 55 txreg2 ausart transmit register 55 txsta2 csrc tx9 txen sync ? brgh trmt tx9d 55 spbrg2 ausart baud rate generator register 55 latg u2od u1od ? latg4 latg3 latg2 latg1 latg0 54 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous transmission. pic18f85j11 family ds39774c-page 244 preliminary ? 2007 microchip technology inc. 18.3.2 ausart asynchronous receiver the receiver block diagram is shown in figure 18-4. the data is received on the rx2 pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . this mode would typically be used in rs-232 systems. to set up an asynchronous reception: 1. initialize the spbrg2 register for the appropriate baud rate. set or clear the brgh bit, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit, sync, and setting bit, spen. 3. if interrupts are desired, set enable bit, rc2ie. 4. if 9-bit reception is desired, set bit, rx9. 5. enable the reception by setting bit, cren. 6. flag bit, rc2if, will be set when reception is complete and an interrupt will be generated if enable bit, rc2ie, was set. 7. read the rcsta2 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg2 register. 9. if any error occurred, clear the error by clearing enable bit, cren. 10. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. 18.3.3 setting up 9-bit mode with address detect this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrg2 register for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are required, set the rcen bit and select the desired priority level with the rc2ip bit. 4. set the rx9 bit to enable 9-bit reception. 5. set the adden bit to enable address detect. 6. enable reception by setting the cren bit. 7. the rc2if bit will be set when reception is complete. the interrupt will be acknowledged if the rc2ie and gie bits are set. 8. read the rcsta2 register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. read rcreg2 to determine if the device is being addressed. 10. if any error occurred, clear the cren bit. 11. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and interrupt the cpu. figure 18-4: ausart recei ve block diagram x64 baud rate clk baud rate generator rx2 pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg2 register fifo interrupt rc2if rc2ie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? spbrg2 or 4 ? 2007 microchip technology inc. preliminary ds39774c-page 245 pic18f85j11 family figure 18-5: asynchronous reception table 18-5: registers associated with asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx2 (pin) rcv buffer reg rcv shift reg read rcv buffer reg rcreg2 rc2if (interrupt flag) oerr bit cren word 1 rcreg2 word 2 rcreg2 stop bit note: this timing diagram shows three words appearing on the rx2 input. the rcreg2 (ausart receive register) is read after the third word, causing the oerr (overrun error) bit to be set. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir3 ? ? rc2if tx2if ? ccp2if ccp1if ?53 pie3 ? ? rc2ie tx2ie ? ccp2ie ccp1ie ?53 ipr3 ? ? rc2ip tx2ip ? ccp2ip ccp1ip ?53 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 55 rcreg2 ausart receive register 55 txsta2 csrc tx9 txen sync ?brgh trmt tx9d 55 spbrg2 ausart baud rate generator register 55 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception. pic18f85j11 family ds39774c-page 246 preliminary ? 2007 microchip technology inc. 18.4 ausart synchronous master mode the synchronous master mode is entered by setting the csrc bit (txsta2<7>). in this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit, sync (txsta2<4>). in addition, enable bit, spen (rcsta2<7>), is set in order to configure the tx2 and rx2 pins to ck2 (clock) and dt2 (data) lines, respectively. the master mode indicates that the processor transmits the master clock on the ck2 line. 18.4.1 ausart synchronous master transmission the ausart transmitter block diagram is shown in figure 18-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg2. the txreg2 register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg2 (if available). once the txreg2 register transfers the data to the tsr register (occurs in one t cycle ), the txreg2 is empty and the tx2if flag bit (pir3<4>) is set. the interrupt can be enabled or disabled by setting or clear- ing the interrupt enable bit, tx2ie (pie3<4>). tx2if is set regardless of the state of enable bit, tx2ie; it cannot be cleared in software. it will reset only when new data is loaded into the txreg2 register. while flag bit, tx2if, indicates the status of the txreg2 register, another bit, trmt (txsta2<1>), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr is empty. no interrupt logic is tied to this bit so the user has to poll this bit in order to deter- mine if the tsr register is empty. the tsr is not mapped in data memory so it is not available to the user. to set up a synchronous master transmission: 1. initialize the spbrg2 register for the appropriate baud rate. 2. enable the synchronous master serial port by setting bits, sync, spen and csrc. 3. if interrupts are desired, set enable bit, tx2ie. 4. if 9-bit transmission is desired, set bit, tx9. 5. enable the transmission by setting bit, txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg2 register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 18-6: synchronous transmission bit 0 bit 1 bit 7 word 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rx2/dt2 pin tx2/ck2 pin write to txreg2 reg tx2if bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrg2 = 0 ; continuous transmission of two 8-bit words. ? 2007 microchip technology inc. preliminary ds39774c-page 247 pic18f85j11 family figure 18-7: synchronous transmissi on (through txen) table 18-6: registers associated with synchronous master transmission rx2/dt2 pin tx2/ck2 pin write to txreg2 reg tx2if bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir3 ? ? rc2if tx2if ? ccp2if ccp1if ?53 pie3 ? ? rc2ie tx2ie ? ccp2ie ccp1ie ?53 ipr3 ? ? rc2ip tx2ip ? ccp2ip ccp1ip ?53 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 55 txreg2 ausart transmit register 55 txsta2 csrc tx9 txen sync ? brgh trmt tx9d 55 spbrg2 ausart baud rate generator register 55 latg u2od u1od ? latg4 latg3 latg2 latg1 latg0 54 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master transmission. pic18f85j11 family ds39774c-page 248 preliminary ? 2007 microchip technology inc. 18.4.2 ausart synchronous master reception once synchronous mode is selected, reception is enabled by setting either the single receive enable bit, sren (rcsta2<5>), or the continuous receive enable bit, cren (rcsta2<4>). data is sampled on the rx2 pin on the falling edge of the clock. if enable bit, sren, is set, only a single word is received. if enable bit, cren, is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. to set up a synchronous master reception: 1. initialize the spbrg2 register for the appropriate baud rate. 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, set enable bit, rc2ie. 5. if 9-bit reception is desired, set bit, rx9. 6. if a single reception is required, set bit, sren. for continuous reception, set bit, cren. 7. interrupt flag bit, rc2if, will be set when reception is complete and an interrupt will be generated if the enable bit, rc2ie, was set. 8. read the rcsta2 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg2 register. 10. if any error occurred, clear the error by clearing bit, cren. 11. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 18-8: synchronous reception (master mode, sren) table 18-7: registers associated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir3 ? ? rc2if tx2if ? ccp2if ccp1if ?53 pie3 ? ? rc2ie tx2ie ? ccp2ie ccp1ie ?53 ipr3 ? ? rc2ip tx2ip ? ccp2ip ccp1ip ?53 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 55 rcreg2 ausart receive register 55 txsta2 csrc tx9 txen sync ? brgh trmt tx9d 55 spbrg2 ausart baud rate generator register 55 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master reception. cren bit rx2/dt2 pin tx2/ck2 pin write to bit sren sren bit rc2if bit (interrupt) read rcreg2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? q1 q2 q3 q4 note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . ? 2007 microchip technology inc. preliminary ds39774c-page 249 pic18f85j11 family 18.5 ausart synchronous slave mode synchronous slave mode is entered by clearing bit, csrc (txsta2<7>). this mode differs from the synchronous master mode in that the shift clock is supplied externally at the ck2 pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in any low-power mode. 18.5.1 ausart synchronous slave transmit the operation of the synchronous master and slave modes are identical except in the case of the sleep mode. if two words are written to the txreg2 and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in the txreg2 register. c) flag bit, tx2if, will not be set. d) when the first word has been shifted out of tsr, the txreg2 register will transfer the second word to the tsr and flag bit, tx2if, will now be set. e) if enable bit, tx2ie, is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave transmission: 1. enable the synchronous slave serial port by setting bits, sync and spen, and clearing bit, csrc. 2. clear bits, cren and sren. 3. if interrupts are desired, set enable bit, tx2ie. 4. if 9-bit transmission is desired, set bit, tx9. 5. enable the transmission by setting enable bit, txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg2 register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 18-8: registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir3 ? ? rc2if tx2if ? ccp2if ccp1if ?53 pie3 ? ? rc2ie tx2ie ? ccp2ie ccp1ie ?53 ipr3 ? ? rc2ip tx2ip ? ccp2ip ccp1ip ?53 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 55 txreg2 ausart transmit register 55 txsta2 csrc tx9 txen sync ? brgh trmt tx9d 55 spbrg2 ausart baud rate generator register 55 latg u2od u1od ? latg4 latg3 latg2 latg1 latg0 54 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave transmission. pic18f85j11 family ds39774c-page 250 preliminary ? 2007 microchip technology inc. 18.5.2 ausart synchronous slave reception the operation of the synchronous master and slave modes is identical except in the case of sleep or any idle mode, and bit, sren, which is a ?don?t care? in slave mode. if receive is enabled by setting the cren bit prior to entering sleep or any idle mode, then a word may be received while in this low-power mode. once the word is received, the rsr register will transfer the data to the rcreg2 register. if the rc2ie enable bit is set, the interrupt generated will wake the chip from the low-power mode. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits, sync and spen, and clearing bit, csrc. 2. if interrupts are desired, set enable bit, rc2ie. 3. if 9-bit reception is desired, set bit, rx9. 4. to enable reception, set enable bit, cren. 5. flag bit, rc2if, will be set when reception is complete. an interrupt will be generated if enable bit, rc2ie, was set. 6. read the rcsta2 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg2 register. 8. if any error occurred, clear the error by clearing bit, cren. 9. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 18-9: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir3 ? ?rc2if tx2if ? ccp2if ccp1if ?53 pie3 ? ? rc2ie tx2ie ? ccp2ie ccp1ie ?53 ipr3 ? ? rc2ip tx2ip ? ccp2ip ccp1ip ?53 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 55 rcreg2 ausart receive register 55 txsta2 csrc tx9 txen sync ? brgh trmt tx9d 55 spbrg2 ausart baud rate generator register 55 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave reception. ? 2007 microchip technology inc. preliminary ds39774c-page 251 pic18f85j11 family 19.0 10-bit analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has 12 inputs for all pic18f85j11 family devices. this module allows conversion of an analog input signal to a corresponding 10-bit digital number. the module has five registers: ? a/d result register high byte (adresh) ? a/d result register low byte (adresl) ? a/d control register 0 (adcon0) ? a/d control register 1 (adcon1) ? a/d control register 2 (adcon2) the adcon0 register, shown in register 19-1, controls the operation of the a/d module. the adcon1 register, shown in register 19-2, configures the functions of the port pins. the adcon2 register, shown in register 19-3, configures the a/d clock source, programmed acquisition time and justification. register 19-1: adcon0: a/d control register 0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcal ? chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 adcal: a/d calibration bit 1 = calibration is performed on next a/d conversion 0 = normal a/d converter operation (no calibration is performed) bit 6 unimplemented: read as ? 0 ? bit 5-2 chs3:chs0: analog channel select bits 0000 = channel 00 (an0) 0001 = channel 01 (an1) 0010 = channel 02 (an2) 0011 = channel 03 (an3) 0100 = channel 04 (an4) 0101 = channel 05 (an5) 0110 = channel 06 (an6) 0111 = channel 07 (an7) 1000 = channel 08 (an8) 1001 = channel 09 (an9) 1010 = channel 10 (an10) 1011 = channel 11 (an11) 11xx = unused bit 1 go/done : a/d conversion status bit when adon = 1 : 1 = a/d conversion in progress 0 = a/d idle bit 0 adon: a/d on bit 1 = a/d converter module is enabled 0 = a/d converter module is disabled pic18f85j11 family ds39774c-page 252 preliminary ? 2007 microchip technology inc. register 19-2: adcon1: a/d control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5 vcfg1: voltage reference configuration bit (v ref - source) 1 =v ref - (an2) 0 =av ss bit 4 vcfg0: voltage reference configuration bit (v ref + source) 1 =v ref + (an3) 0 =av dd bit 3-0 pcfg3:pcfg0: a/d port configuration control bits: a = analog input d = digital i/o pcfg<3:0> an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 0000 aaaaaaaaaaaa 0001 aaaaaaaaaaaa 0010 aaaaaaaaaaaa 0011 aaaaaaaaaaaa 0100 daaaaaaaaaaa 0101 ddaaaaaaaaaa 0110 dddaaaaaaaaa 0111 ddddaaaaaaaa 1000 dddddaaaaaaa 1001 ddddddaaaaaa 1010 dddddddaaaaa 1011 ddddddddaaaa 1100 dddddddddaaa 1101 ddddddddddaa 1110 ddddddddddda 1111 dddddddddddd ? 2007 microchip technology inc. preliminary ds39774c-page 253 pic18f85j11 family register 19-3: adcon2: a/d control register 2 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6 unimplemented: read as ? 0 ? bit 5-3 acqt2:acqt0: a/d acquisition time select bits 111 = 20 t ad 110 = 16 t ad 101 = 12 t ad 100 = 8 t ad 011 = 6 t ad 010 = 4 t ad 001 = 2 t ad 000 = 0 t ad (1) bit 2-0 adcs2:adcs0: a/d conversion clock select bits 111 = f rc (clock derived from a/d rc oscillator) (1) 110 = f osc /64 101 = f osc /16 100 = f osc /4 011 = f rc (clock derived from a/d rc oscillator) (1) 010 = f osc /32 001 = f osc /8 000 = f osc /2 note 1: if the a/d f rc clock source is selected, a delay of one t cy (instruction cycle) is added before the a/d clock starts. this allows the sleep instruction to be executed before starting a conversion. pic18f85j11 family ds39774c-page 254 preliminary ? 2007 microchip technology inc. the analog reference voltage is software selectable to either the device?s positive and negative supply voltage (av dd and av ss ), or the voltage level on the ra3/an3/v ref + and ra2/an2/v ref - pins. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to operate in sleep, the a/d conversion clock must be derived from the a/d?s internal rc oscillator. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. each port pin associated with the a/d converter can be configured as an analog input or as a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is com- plete, the result is loaded into the adresh:adresl register pair, the go/done bit (adcon0<1>) is cleared and the a/d interrupt flag bit, adif, is set. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion in progress is aborted. the value in the adresh:adresl register pair is not modified for a power-on reset. these registers will contain unknown data after a power-on reset. the block diagram of the a/d module is shown in figure 19-1. figure 19-1: a/d block diagram (1) (input voltage) v ain v ref + reference voltage v dd vcfg1:vcfg0 chs3:chs0 an7 an6 an4 an3 an2 an1 an0 0111 0110 0100 0011 0010 0001 0000 10-bit a/d v ref - v ss converter an11 an10 an9 an8 1011 1010 1001 1000 note 1: i/o pins have diode protection to v dd and v ss . an5 0101 ? 2007 microchip technology inc. preliminary ds39774c-page 255 pic18f85j11 family after the a/d module has been configured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as inputs. to determine acquisition time, see section 19.1 ?a/d acquisition requirements? . after this acquisition time has elapsed, the a/d conversion can be started. an acquisition time can be programmed to occur between setting the go/done bit and the actual start of the conversion. the following steps should be followed to do an a/d conversion: 1. configure the a/d module: ? configure analog pins, voltage reference and digital i/o (adcon1) ? select a/d input channel (adcon0) ? select a/d acquisition time (adcon2) ? select a/d conversion clock (adcon2) ? turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): ? clear adif bit ? set adie bit ? set gie bit 3. wait the required acquisition time (if required). 4. start conversion: ? set go/done bit (adcon0<1>) 5. wait for a/d conversion to complete, by either: ? polling for the go/done bit to be cleared or ? waiting for the a/d interrupt 6. read a/d result registers (adresh:adresl); clear adif bit, if required. 7. for next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before next acquisition starts. figure 19-2: analog input model v ain c pin r s anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = 25 pf v ss 6v sampling switch (k ) 5v 4v 3v 2v 123 4 v dd 100 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions = sampling switch resistance r ss pic18f85j11 family ds39774c-page 256 preliminary ? 2007 microchip technology inc. 19.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 19-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5 k . after the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. to calculate the minimum acquisition time, equation 19-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. equation 19-3 shows the calculation of the minimum required acquisition time, t acq . this calculation is based on the following application system assumptions: c hold =25 pf rs = 2.5 k conversion error 1/2 lsb v dd =3v rss = 2 k temperature = 85c (system max.) equation 19-1: a/d acquisition time equation 19-2: a/d minimum charging time equation 19-3: calculating the minimum required acquisition time note: when the conversion is started, the holding capacitor is disconnected from the input pin. t acq = amplifier settling time + holding capacitor charging time + temperature coefficient =t amp + t c + t coff v hold = (v ref ? (v ref /2048)) ? (1 ? e (-t c /c hold (r ic + r ss + r s )) ) or t c = -(c hold )(r ic + r ss + r s ) ln(1/2048) t acq =t amp + t c + t coff t amp =0.2 s t coff = (temp ? 25 c)(0.02 s/ c) (85 c ? 25 c)(0.02 s/ c) 1.2 s temperature coefficient is only required for temperatures > 25 c. below 25 c, t coff = 0 ms. t c = -(c hold )(r ic + r ss + r s ) ln(1/2048) s -(25 pf) (1 k + 2 k + 2.5 k ) ln(0.0004883) s 1.05 s t acq = 0.2 s + 1 s + 1.2 s 2.4 s ? 2007 microchip technology inc. preliminary ds39774c-page 257 pic18f85j11 family 19.2 selecting and configuring automatic acquisition time the adcon2 register allows the user to select an acquisition time that occurs each time the go/done bit is set. when the go/done bit is set, sampling is stopped and a conversion begins. the user is responsible for ensur- ing the required acquisition time has passed between selecting the desired input channel and setting the go/done bit. this occurs when the acqt2:acqt0 bits (adcon2<5:3>) remain in their reset state (? 000 ?) and is compatible with devices that do not offer programmable acquisition times. if desired, the acqt bits can be set to select a programmable acquisition time for the a/d module. when the go/done bit is set, the a/d module contin- ues to sample the input for the selected acquisition time, then automatically begins a conversion. since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the go/done bit. in either case, when the conversion is completed, the go/done bit is cleared, the adif flag is set and the a/d begins sampling the currently selected channel again. if an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 19.3 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 11 t ad per 10-bit conversion. the source of the a/d conversion clock is software selectable. there are seven possible options for t ad : ?2 t osc ?4 t osc ?8 t osc ?16 t osc ?32 t osc ?64 t osc ? internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be as short as possible but greater than the minimum t ad (see parameter 130 in table 25-24 for more information). table 19-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. table 19-1: t ad vs. device operating frequencies 19.4 configuring analog port pins the adcon1, trisa, trisf and trish registers control the operation of the a/d port pins. the port pins needed as analog inputs must have their correspond- ing tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs3:chs0 bits and the tris bits. ad clock source (t ad )maximum device frequency operation adcs2:adcs0 2 t osc 000 2.86 mhz 4 t osc 100 5.71 mhz 8 t osc 001 11.43 mhz 16 t osc 101 22.86 mhz 32 t osc 010 40.0 mhz 64 t osc 110 40.0 mhz rc (1) x11 1.00 mhz (2) note 1: the rc source has a typical t ad time of 4s. 2: for device frequencies above 1 mhz, the device must be in sleep mode for the entire conversion or the a/d accuracy may be out of specification. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs will convert an analog input. analog levels on a digitally configured input will be accurately converted. 2: analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device?s specification limits. pic18f85j11 family ds39774c-page 258 preliminary ? 2007 microchip technology inc. 19.5 a/d conversions figure 19-3 shows the operation of the a/d converter after the go/done bit has been set and the acqt2:acqt0 bits are cleared. a conversion is started after the following instruction to allow entry into sleep mode before the conversion begins. figure 19-4 shows the operation of the a/d converter after the go/done bit has been set, the acqt2:acqt0 bits have been set to ? 010 ? and a 4t ad acquisition time has been selected before the conversion starts. clearing the go/done bit during a conversion will abort the current conversion. the a/d result register pair will not be updated with the partially completed a/d conversion sample. this means the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is completed or aborted, a 2t ad wait is required before the next acquisition can be started. after this wait, acquisition on the selected channel is automatically started. 19.6 use of the ccp2 trigger an a/d conversion can be started by the ?special event trigger? of the ccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be pro- grammed as ? 1011 ? and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d acquisition and conversion, and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to auto- matically repeat the a/d acquisition period with minimal software overhead (moving adresh/adresl to the desired location). the appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate t acq time is selected before the special event trigger sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), the special event trigger will be ignored by the a/d module but will still reset the timer1 (or timer3) counter. figure 19-3: a/d conversion t ad cycles (acqt2:acqt0 = 000 , t acq = 0 ) figure 19-4: a/d conversion t ad cycles (acqt2:acqt0 = 010 , t acq = 4 t ad ) note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go/done bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy ? t ad next q4: adresh/adresl are loaded, go/done bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 1 2 3 4 5 6 7 8 11 set go/done bit (holding capacitor is disconnected) 9 10 next q4: adresh:adresl are loaded, go/done bit is cleared, adif bit is set, holding capacitor is reconnected to analog input. conversion starts 1 2 3 4 (holding capacitor continues acquiring input) t acqt cycles t ad cycles automatic acquisition time b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 ? 2007 microchip technology inc. preliminary ds39774c-page 259 pic18f85j11 family 19.7 a/d converter calibration the a/d converter in the pic18f85j11 family of devices includes a self-calibration feature which com- pensates for any offset generated within the module. the calibration process is automated and is initiated by setting the adcal bit (adcon0<7>). the next time the go/done bit is set, the module will perform a ?dummy? conversion (that is, with reading none of the input channels) and store the resulting value internally to compensate for offset. thus, subsequent offsets will be compensated. the calibration process assumes that the device is in a relatively steady-state operating condition. if a/d calibration is used, it should be performed after each device reset or if there are other major changes in operating conditions. 19.8 operation in power-managed modes the selection of the automatic acquisition time and a/d conversion clock is determined in part by the clock source and frequency while in a power-managed mode. if the a/d is expected to operate while the device is in a power-managed mode, the acqt2:acqt0 and adcs2:adcs0 bits in adcon2 should be updated in accordance with the power-managed mode clock that will be used. after the power-managed mode is entered (either of the power-managed run modes), an a/d acquisition or conversion may be started. once an acquisition or conversion is started, the device should continue to be clocked by the same power-managed mode clock source until the conversion has been com- pleted. if desired, the device may be placed into the corresponding power-managed idle mode during the conversion. if the power-managed mode clock frequency is less than 1 mhz, the a/d rc clock source should be selected. operation in the sleep mode requires the a/d rc clock to be selected. if bits, acqt2:acqt0, are set to ? 000 ? and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the sleep instruction and entry to sleep mode. the idlen and scs<1:0> bits in the osccon register must have already been cleared prior to starting the conversion. table 19-2: summary of a/d registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir1 pspif adif rc1if tx1if sspif ? tmr2if tmr1if 53 pie1 pspie adie rc1ie tx1ie sspie ? tmr2ie tmr1ie 53 ipr1 pspip adip rc1ip tx1ip sspip ? tmr2ip tmr1ip 53 pir3 ? ? rc2if tx2if ? ccp2if ccp1if ?53 pie3 ? ? rc2ie tx2ie ? ccp2ie ccp1ie ?53 ipr3 ? ? rc2ip tx2ip ? ccp2ip ccp1ip ?53 adresh a/d result register high byte 53 adresl a/d result register low byte 53 adcon0 adcal ? chs3 chs2 chs1 chs0 go/done adon 53 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 53 adcon2 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 53 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 54 porta ra7 (1) ra6 (1) ra5 ra4 ra3 ra2 ra1 ra0 54 trisa trisa7 (1) trisa6 (1) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 54 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 ?54 trisf trisf5 trisf4 trisf5 t risf4 trisf3 trisf2 trisf1 ?54 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for a/d conversion. note 1: ra6/ra7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (fosc2 configuration bit = 0 ); otherwise, they are disabled and these bits read as ? 0 ?. pic18f85j11 family ds39774c-page 260 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. preliminary ds39774c-page 261 pic18f85j11 family 20.0 comparator module the analog comparator module contains two comparators that can be configured in a variety of ways. the inputs can be selected from the analog inputs multiplexed with pins rf1 through rf6, as well as the on-chip voltage reference (see section 21.0 ?comparator voltage reference module? ). the digi- tal outputs (normal or inverted) are available at the pin level and can also be read through the control register. the cmcon register (register 20-1) selects the comparator input and output configuration. block diagrams of the various comparator configurations are shown in figure 20-1. register 20-1: cmcon: comparat or module control register r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 c2out c1out c2inv c1inv cis cm2 cm1 cm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 c2out : comparator 2 output bit when c2inv = 0 : 1 = c2 v in + > c2 v in - 0 = c2 v in + < c2 v in - when c2inv = 1 : 1 = c2 v in + < c2 v in - 0 = c2 v in + > c2 v in - bit 6 c1out : comparator 1 output bit when c1inv = 0 : 1 = c1 v in + > c1 v in - 0 = c1 v in + < c1 v in - when c1inv = 1 : 1 = c1 v in + < c1 v in - 0 = c1 v in + > c1 v in - bit 5 c2inv : comparator 2 output inversion bit 1 = c2 output inverted 0 = c2 output not inverted bit 4 c1inv : comparator 1 output inversion bit 1 = c1 output inverted 0 = c1 output not inverted bit 3 cis : comparator input switch bit when cm2:cm0 = 110 : 1 =c1 v in - connects to rf5/an10/cv ref c2 v in - connects to rf3/an8 0 =c1 v in - connects to rf6/an11 c2 v in - connects to rf4/an9 bit 2-0 cm2:cm0 : comparator mode bits figure 20-1 shows the comparator modes and the cm2:cm0 bit settings. pic18f85j11 family ds39774c-page 262 preliminary ? 2007 microchip technology inc. 20.1 comparator configuration there are eight modes of operation for the compara- tors, shown in figure 20-1. bits cm2:cm0 of the cmcon register are used to select these modes. the trisf register controls the data direction of the comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in section 25.0 ?electrical characteristics? . figure 20-1: comparator i/o operating modes note: comparator interrupts should be disabled during a comparator mode change; otherwise, a false interrupt may occur. c1 v in - v in + off (read as ? 0 ?) comparator outputs disabled a a cm2:cm0 = 000 c2 v in - v in + off (read as ? 0 ?) a a c1 v in - v in + c1out two independent comparators a a cm2:cm0 = 010 c2 v in - v in + c2out a a c1 v in - v in + c1out two common reference comparators a a cm2:cm0 = 100 c2 v in - v in + c2out a d c2 v in - v in + off (read as ? 0 ?) one independent comparator with output d d cm2:cm0 = 001 c1 v in - v in + c1out a a c1 v in - v in + off (read as ? 0 ?) comparators off (por default value) d d cm2:cm0 = 111 c2 v in - v in + off (read as ? 0 ?) d d c1 v in - v in + c1out four inputs multiplexed to two comparators a a cm2:cm0 = 110 c2 v in - v in + c2out a a from v ref module cis = 0 cis = 1 cis = 0 cis = 1 c1 v in - v in + c1out two common reference comparators with outputs a a cm2:cm0 = 101 c2 v in - v in + c2out a d a = analog input, port reads zeros always d = digital input cis (cmcon<3>) is the comparator input switch cv ref c1 v in - v in + c1out two independent comparators with outputs a a cm2:cm0 = 011 c2 v in - v in + c2out a a rf1/an6/c2out* rf2/an7/c1out* * setting the trisf<2:1> bits will disable the comparator outputs by configuring the pins as inputs. rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf2/an7/c1out* rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf1/an6/c2out* rf2/an7/c1out* rf6/an11 rf5/an10 rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref ? 2007 microchip technology inc. preliminary ds39774c-page 263 pic18f85j11 family 20.2 comparator operation a single comparator is shown in figure 20-2, along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in -, the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 20-2 represent the uncertainty due to input offsets and response time. 20.3 comparator reference depending on the comparator operating mode, either an external or internal voltage reference may be used. the analog signal present at v in - is compared to the signal at v in + and the digital output of the comparator is adjusted accordingly (figure 20-2). figure 20-2: single comparator 20.3.1 external reference signal when external voltage references are used, the comparator module can be configured to have the com- parators operate from the same or different reference sources. however, threshold detector applications may require the same reference. the reference signal must be between v ss and v dd and can be applied to either pin of the comparator(s). 20.3.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference from the comparator voltage reference module. this module is described in more detail in section 21.0 ?comparator voltage reference module? . the internal reference is only available in the mode where four inputs are multiplexed to two comparators (cm2:cm0 = 110 ). in this mode, the internal voltage reference is applied to the v in + pin of both comparators. 20.4 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. if the internal ref- erence is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. otherwise, the maximum delay of the comparators should be used (see section 25.0 ?electrical characteristics? ). 20.5 comparator outputs the comparator outputs are read through the cmcon register. these bits are read-only. the comparator outputs may also be directly output to the rf1 and rf2 i/o pins. when enabled, multiplexors in the output path of the rf1 and rf2 pins will switch and the output of each pin will be the unsynchronized output of the comparator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. figure 20-3 shows the comparator output block diagram. the trisf bits will still function as output enables/ disables for the rf1 and rf2 pins while in this mode. the polarity of the comparator outputs can be changed using the c2inv and c1inv bits (cmcon<5:4>). ? + v in + v in - output output v in - v in + note 1: when reading the port register, all pins configured as analog inputs will read as ? 0 ?. pins configured as digital inputs will convert an analog input according to the schmitt trigger input specification. 2: analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified. pic18f85j11 family ds39774c-page 264 preliminary ? 2007 microchip technology inc. figure 20-3: comparator output block diagram 20.6 comparator interrupts the comparator interrupt flag is set whenever there is a change in the output value of either comparator. software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, to determine the actual change that occurred. the cmif bit (pir2<6>) is the comparator interrupt flag. the cmif bit must be reset by clearing it. since it is also possible to write a ? 1 ? to this register, a simulated interrupt may be initiated. both the cmie bit (pie2<6>) and the peie bit (intcon<6>) must be set to enable the interrupt. in addition, the gie bit (intcon<7>) must also be set. if any of these bits are clear, the interrupt is not enabled, though the cmif bit will still be set if an interrupt condition occurs. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of cmcon will end the mismatch condition. b) clear flag bit, cmif. a mismatch condition will continue to set flag bit, cmif. reading cmcon will end the mismatch condition and allow flag bit, cmif, to be cleared. 20.7 comparator operation during sleep when a comparator is active and the device is placed in sleep mode, the comparator remains active and the interrupt is functional if enabled. this interrupt will wake-up the device from sleep mode when enabled. each operational comparator will consume additional current, as shown in the comparator specifications. to minimize power consumption while in sleep mode, turn off the comparators (cm2:cm0 = 111 ) before entering sleep. if the device wakes up from sleep, the contents of the cmcon register are not affected. 20.8 effects of a reset a device reset forces the cmcon register to its reset state, causing the comparator modules to be turned off (cm2:cm0 = 111) . however, the input pins (rf3 through rf6) are configured as analog inputs by default on device reset. the i/o configuration for these pins is determined by the setting of the pcfg3:pcfg0 bits (adcon1<3:0>). therefore, device current is minimized when analog inputs are present at reset time. dq en to rf1 or rf2 pin bus data set multiplex cmif bit + port pins read cmcon reset from other comparator cxinv dq en cl - note: if a change in the cmcon register (c1out or c2out) should occur when a read operation is being executed (start of the q2 cycle), then the cmif (pir2<6>) interrupt flag may not get set. ? 2007 microchip technology inc. preliminary ds39774c-page 265 pic18f85j11 family 20.9 analog input connection considerations a simplified circuit for an analog input is shown in figure 20-4. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up condition may occur. a maximum source impedance of 10 k is recommended for the analog sources. any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. figure 20-4: comparator analog input model table 20-1: registers associated with comparator module va r s < 10k a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r ic i leakage 500 na v ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance va = analog voltage comparator input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 51 pir2 oscfif cmif ? ? bclif lvdif tmr3if ?53 pie2 oscfie cmie ? ? bclie lvdie tmr3ie ?53 ipr2 oscfip cmip ? ? bclip lvdip tmr3ip ?53 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 53 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 53 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 ?54 latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 ?54 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 ?54 legend: ? = unimplemented, read as ? 0 ?. shaded cells are unused by the comparator module. pic18f85j11 family ds39774c-page 266 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. preliminary ds39774c-page 267 pic18f85j11 family 21.0 comparator voltage reference module the comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. a block diagram of the module is shown in figure 21-1. the resistor ladder is segmented to provide two ranges of cv ref values and has a power-down function to conserve power when the reference is not being used. the module?s supply reference can be provided from either device v dd /v ss or an external voltage reference. 21.1 configuring the comparator voltage reference the comparator voltage reference module is controlled through the cvrcon register (register 21-1). the comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. the range to be used is selected by the cvrr bit (cvrcon<5>). the primary difference between the ranges is the size of the steps selected by the cv ref selection bits (cvr3:cvr0), with one range offering finer resolution. the equations used to calculate the output of the comparator voltage reference are as follows: if cvrr = 1 : cv ref = ((cvr3:cvr0)/24) x (cv rsrc ) if cvrr = 0 : cv ref =(cv rsrc /4) + ((cvr3:cvr0)/32) x (cv rsrc ) the comparator reference supply voltage can come from either v dd and v ss , or the external v ref + and v ref - that are multiplexed with ra2 and ra3. the voltage source is selected by the cvrss bit (cvrcon<4>). the settling time of the comparator voltage reference must be considered when changing the cv ref output (see table 25-3 in section 25.0 ?electrical characteristics? ). register 21-1: cvrcon: comparator vo ltage reference control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe (1) cvrr cvrss cvr3 cvr2 cvr1 cvr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 cvren : comparator voltage reference enable bit 1 =cv ref circuit powered on 0 =cv ref circuit powered down bit 6 cvroe : comparator v ref output enable bit (1) 1 =cv ref voltage level is also output on the rf5/an10/cv ref pin 0 =cv ref voltage is disconnected from the rf5/an10/cv ref pin bit 5 cvrr : comparator v ref range selection bit 1 = 0 to 0.667 cv rsrc , with cv rsrc /24 step size (low range) 0 = 0.25 cv rsrc to 0.75 cv rsrc , with cv rsrc /32 step size (high range) bit 4 cvrss : comparator v ref source selection bit 1 = comparator reference source, cv rsrc = (v ref +) ? (v ref -) 0 = comparator reference source, cv rsrc = v dd ? v ss bit 3-0 cvr3:cvr0: comparator v ref value selection bits (0 (cvr3:cvr0) 15) when cvrr = 1 : cv ref = ((cvr3:cvr0)/24) ? (cv rsrc ) when cvrr = 0 : cv ref = (cv rsrc /4) + ((cvr3:cvr0)/32) ? (cv rsrc ) note 1: cvroe overrides the trisf<5> bit setting. pic18f85j11 family ds39774c-page 268 preliminary ? 2007 microchip technology inc. figure 21-1: comparator voltage reference block diagram 21.2 comparator voltage reference accuracy/error the full range of comparator voltage reference cannot be realized due to the construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 21-1) keep cv ref from approaching the reference source rails. the voltage reference is derived from the reference source; therefore, the cv ref output changes with fluctuations in that source. the tested absolute accuracy of the voltage reference can be found in section 25.0 ?electrical characteristics? . 21.3 operation during sleep when the device wakes up from sleep through an interrupt or a watchdog timer time-out, the contents of the cvrcon register are not affected. to minimize current consumption in sleep mode, the comparator voltage reference should be disabled. 21.4 effects of a reset a device reset disables the comparator voltage reference by clearing bit, cvren (cvrcon<7>). this reset also disconnects the reference from the ra2 pin by clearing bit, cvroe (cvrcon<6>) and selects the high-voltage range by clearing bit, cvrr (cvrcon<5>). the cvr<3:0> value select bits are also cleared. 21.5 connection considerations the comparator voltage reference module operates independently of the comparator module. the output of the reference generator may be connected to the rf5 pin if the cvroe bit is set. enabling the voltage refer- ence output onto ra2 when it is configured as a digital input will increase current consumption. connecting rf5 as a digital output with cvrss enabled will also increase current consumption. the rf5 pin can be used as a simple d/a output with limited drive capability. due to the limited current drive capability, a buffer must be us ed on the comparator volt- age reference output for external connections to v ref . figure 21-2 shows an example buffering technique. 16-to-1 mux cvr3:cvr0 8r r cvren cvrss = 0 v dd v ref + cvrss = 1 8r cvrss = 0 v ref - cvrss = 1 r r r r r r 16 steps cvrr cv ref ? 2007 microchip technology inc. preliminary ds39774c-page 269 pic18f85j11 family figure 21-2: comparator voltage reference output buffer example table 21-1: registers associated with comparator voltage reference cv ref output + ? cv ref module voltage reference output impedance r (1) rf5 note 1: r is dependent upon the comparator voltage reference bits, cvrcon<5> and cvrcon<3:0>. pic18f85j11 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 53 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 53 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 ?54 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used with the comparator voltage reference. pic18f85j11 family ds39774c-page 270 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. preliminary ds39774c-page 271 pic18f85j11 family 22.0 special features of the cpu pic18f85j11 family devices include several features intended to maximize reliability and minimize cost through elimination of external components. these are: ? oscillator selection ? resets: - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) ? interrupts ? watchdog timer (wdt) ? fail-safe clock monitor ? two-speed start-up ? code protection ? in-circuit serial programming the oscillator can be configured for the application depending on frequency, power, accuracy and cost. all of the options are discussed in detail in section 2.0 ?oscillator configurations? . a complete discussion of device resets and interrupts is available in previous sections of this data sheet. in addition to their power-up and oscillator start-up timers provided for resets, the pic18f85j11 family of devices have a configurable watchdog timer which is controlled in software. the inclusion of an internal rc oscillator also provides the additional benefits of a fail-safe clock monitor (fscm) and two-speed start-up. fscm provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. two-speed start-up enables code to be executed almost immediately on start-up while the primary clock source completes its start-up delays. all of these features are enabled and configured by setting the appropriate configuration register bits. 22.1 configuration bits the configuration bits can be programmed (read as ? 0 ?), or left unprogrammed (read as ? 1 ?), to select various device configurations. these bits are mapped starting at program memory location 300000h. a complete list is shown in table 22-2. a detailed explanation of the various bit functions is provided in register 22-1 through register 22-6. 22.1.1 considerations for configuring the pic18f85j11 family devices devices of the pic18f85j11 family do not use persistent memory registers to store configuration information. the configuration bytes are implemented as volatile memory which means that configuration data must be programmed each time the device is powered up. configuration data is stored in the four words at the top of the on-chip program memory space, known as the flash configuration words. it is stored in program memory in the same order shown in table 22-2, with config1l at the lowest address and config3h at the highest. the data is automatically loaded in the proper configuration registers during device power-up. when creating applications for these devices, users should always specifically allocate the location of the flash configuration word for configuration data. this is to make certain that program code is not stored in this address when the code is compiled. the volatile memory cells used for the configuration bits always reset to ? 1 ? on power-on resets. for all other types of reset events, the previously programmed values are maintained and used without reloading from program memory. the four most significant bits of config1h, config2h and config3h in program memory should also be ? 1111 ?. this makes these configuration words appear to be nop instructions in the remote event that their locations are ever executed by accident. since configuration bits are not implemented in the corresponding locations, writing ? 1 ?s to these locations has no effect on device operation. to prevent inadvertent configuration changes during code execution, all programmable configuration bits are write-once. after a bit is initially programmed during a power cycle, it cannot be written to again. changing a device configuration requires that power to the device be cycled. table 22-1: mapping of the flash configuration words to the configuration registers configuration byte code space address configuration register address config1l xxxf8h 300000h config1h xxxf9h 300001h config2l xxxfah 300002h config2h xxxfbh 300003h config3l xxxfch 300004h config3h xxxfdh 300005h pic18f85j11 family ds39774c-page 272 preliminary ? 2007 microchip technology inc. table 22-2: configuration bits and device ids file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value (1) 300000h config1l debug xinst stvren ? ? ? ?wdten 111- ---1 300001h config1h ? (2) ? (2) ? (2) ? (2) ? (3) cp0 ? ? ---- 01-- 300002h config2l ieso fcmen ? ? ? fosc2 fosc1 fosc0 11-- -111 300003h config2h ? (2) ? (2) ? (2) ? (2) wdtps3 wdtps2 wdtps1 wdtps0 ---- 1111 300004h config3l (4) wait bw emb1 emb0 eashft ? ? ? 1111 1--- 300005h config3h ? (2) ? (2) ? (2) ? (2) ? ? ? ccp2mx ---- ---1 3ffffeh devid1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 xxxx xxxx (5) 3fffffh devid2 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 0000 10x1 (5) legend: x = unknown, ? = unimplemented. shaded cells are unimplemented, read as ? 0 ?. note 1: values reflect the unprogrammed state as received from t he factory and following power-on resets. in all other reset states, the configuration bytes maintain their previously programmed states. 2: the value of these bits in program memory should always be ? 1 ?. this ensures that the location is executed as a nop if it is accidentally executed. 3: this bit should always be maintained as ? 0 ?. 4: config3l is implemented in 80-pin devices only. 5: see register 22-7 and register 22-8 for devid values. t hese registers are read-only and cannot be programmed by the user. ? 2007 microchip technology inc. preliminary ds39774c-page 273 pic18f85j11 family register 22-1: config1l: configuration register 1 low (byte address 300000h) r/wo-1 r/wo-1 r/wo-1 u-0 u-0 u-0 u-0 r/wo-1 debug xinst stvren ? ? ? ?wdten bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as ? 0 ? -n = value when device is unprogrammed ?1? = bit is set ?0? = bit is cleared bit 7 debug : background debugger enable bit 1 = background debugger disabled; rb6 and rb7 configured as general purpose i/o pins 0 = background debugger enabled; rb6 and rb7 are dedicated to in-circuit debug bit 6 xinst: extended instruction set enable bit 1 = instruction set extension and indexed addressing mode enabled 0 = instruction set extension and indexed addressing mode disabled (legacy mode) bit 5 stvren : stack overflow/underflow reset enable bit 1 = reset on stack overflow/underflow enabled 0 = reset on stack overflow/underflow disabled bit 4-1 unimplemented: read as ? 0 ? bit 0 wdten: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on swdten bit) register 22-2: config1h: co nfiguration register 1 high (byte address 300001h) u-0 u-0 u-0 u-0 u-0 r/wo-1 u-0 u-0 ? (1) ? (1) ? (1) ? (1) ? (2) cp0 ? ? bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as ? 0 ? -n = value when device is unprogrammed ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented: read as ? 1 ? (1) bit 3 unimplemented: read as ? 0 ? (2) bit 2 cp0: code protection bit 1 = program memory is not code-protected 0 = program memory is code-protected bit 1-0 unimplemented: read as ? 0 ? note 1: the value of these bits in program memory should always be ? 1 ?. this ensures that the location is executed as a nop if it is accidentally executed. 2: this bit should always be maintained as ? 0 ?. pic18f85j11 family ds39774c-page 274 preliminary ? 2007 microchip technology inc. register 22-3: config2l: configuration register 2 low (byte address 300002h) r/wo-1 r/wo-1 u-0 u-0 u-0 r/wo-1 r/wo-1 r/wo-1 ieso fcmen ? ? ? fosc2 fosc1 fosc0 bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as ? 0 ? -n = value when device is unprogrammed ?1? = bit is set ?0? = bit is cleared bit 7 ieso: two-speed start-up (internal/external oscillator switchover) control bit 1 = two-speed start-up enabled 0 = two-speed start-up disabled bit 6 fcmen: fail-safe clock monitor enable bit 1 = fail-safe clock monitor enabled 0 = fail-safe clock monitor disabled bit 5-3 unimplemented: read as ? 0 ? bit 2-0 fosc2:fosc0: oscillator selection bits 111 = osc1/osc2 as primary; ec oscillator with clko function and software controlled pll (ecpll) 110 = osc1/osc2 as primary; ec oscillator with clko function (ec) 101 = osc1/osc2 as primary; hs oscillator with software controlled pll (hspll) 100 = osc1/osc2 as primary; hs oscillator (hs) 011 = intosc with clko as primary; port function on ra7; ec oscillator with clko function and software controlled pll (ecpll) 010 = intosc with clko as primary; port function on ra7; ec oscillator with clko function 001 = intosc as primary with port function on ra6/ra7; hs oscillator with software controlled pll (hspll) 000 = intosc as primary with port function on ra6/ra7; hs oscillator (hs) ? 2007 microchip technology inc. preliminary ds39774c-page 275 pic18f85j11 family register 22-4: config2h: configuration register 2 high (byte address 300003h) u-0 u-0 u-0 u-0 r/wo-1 r/wo-1 r/wo-1 r/wo-1 ? (1) ? (1) ? (1) ? (1) wdtps3 wdtps2 wdtps1 wdtps0 bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as ? 0 ? -n = value when device is unprogrammed ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented: read as ? 1 ? (1) bit 3-0 wdtps3:wdtps0: watchdog timer postscale select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 note 1: the value of these bits in program memory should always be ? 1 ?. this ensures that the location is executed as a nop if it is accidentally executed. pic18f85j11 family ds39774c-page 276 preliminary ? 2007 microchip technology inc. register 22-5: config3l: configuration register 3 low (byte address 300004h) (1) r/wo-1 r/wo-1 r/wo-1 r/wo-1 r/wo-1 u-0 u-0 u-0 wait bw emb1 emb0 eashft ? ? ? bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as ? 0 ? -n = value when device is unprogrammed ?1? = bit is set ?0? = bit is cleared bit 7 wait: external bus wait enable bit 1 = wait selections from memcon.wait<1:0> are unavailable and the device will not wait 0 = wait programmed by memcon.wait<1:0> bit 6 bw: data bus width select bit 1 = 16-bit external bus mode 0 = 8-bit external bus mode bit 5-4 emb1:emb0: external memory bus configuration bits 00 = extended microcontroller mode ? 20-bit address mode 01 = extended microcontroller mode ? 16-bit address mode 10 = extended microcontroller mode ? 12-bit address mode 11 = microcontroller mode ? external bus disabled bit 3 eashft: external address bus shift enable bit 1 = address shifting enabled ? external address bus is shifted to start at 000000h 0 = address shifting disabled ? external address bus reflects the pc value bit 2-0 unimplemented: read as ? 0 ? note 1: config3l and its associated bits are implemented only in 80-pin devices. register 22-6: config3h: configuration register 3 high (byte address 300005h) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/wo-1 ? (1) ? (1) ? (1) ? (1) ? ? ? ccp2mx bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as ? 0 ? -n = value when device is unprogrammed ?1? = bit is set ?0? = bit is cleared bit 7-1 unimplemented: read as ? 1 ? (1) bit 0 ccp2mx: ccp2 mux bit 1 = ccp2 is multiplexed with rc1 0 = ccp2 is multiplexed with re7 in microcontroller mode (all devices) or with rb3 in extended microcontroller mode (80-pin devices only) note 1: the value of these bits in program memory should always be ? 1 ?. this ensures that the location is executed as a nop if it is accidentally executed. ? 2007 microchip technology inc. preliminary ds39774c-page 277 pic18f85j11 family register 22-7: devid1: device id register 1 for pic18f85j11 family devices rrrrrrrr dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 bit 7 bit 0 legend: r = read-only bit bit 7-5 dev2:dev0: device id bits 111 = pic18f85j11 101 = pic18f84j11 100 = pic18f83j11 011 = pic18f65j11 001 = pic18f64j11 000 = pic18f63j11 bit 4-0 rev4:rev0: revision id bits these bits are used to indicate the device revision. register 22-8: devid2: device id register 2 for pic18f85j11 family devices rrrrrrrr dev10 (1) dev9 (1) dev8 (1) dev7 (1) dev6 (1) dev5 (1) dev4 (1) dev3 (1) bit 7 bit 0 legend: r = read-only bit bit 7-0 dev10:dev3: device id bits (1) these bits are used with the dev2:dev0 bits in the device id register 1 to identify the part number. 0011 1001 = pic18f6xj11/8xj11 devices note 1: the values for dev10:dev3 may be shared with other device families. the specific device is always identified by using the entire dev10:dev0 bit sequence. pic18f85j11 family ds39774c-page 278 preliminary ? 2007 microchip technology inc. 22.2 watchdog timer (wdt) for pic18f85j11 family devices, the wdt is driven by the intrc oscillator. when the wdt is enabled, the clock source is also enabled. the nominal wdt period is 4 ms and has the same stability as the intrc oscillator. the 4 ms period of the wdt is multiplied by a 16-bit postscaler. any output of the wdt postscaler is selected by a multiplexor, controlled by the wdtps bits in configuration register 2h. available periods range from 4 ms to 131.072 seconds (2.18 minutes). the wdt and postscaler are cleared whenever a sleep or clrwdt instruction is executed, or a clock failure (primary or timer1 oscillator) has occurred. 22.2.1 control register the wdtcon register (register 22-9) is a readable and writable register. the swdten bit enables or dis- ables wdt operation. this allows software to override the wdten configuration bit and enable the wdt only if it has been disabled by the configuration bit. figure 22-1: wdt block diagram table 22-3: summary of watchdog timer registers note 1: the clrwdt and sleep instructions clear the wdt and postscaler counts when executed. 2: when a clrwdt instruction is executed, the postscaler count will be cleared. register 22-9: wdtcon: watchdog timer control register r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 regslp (1) ? ? ? ? ? ?swdten (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 regslp: voltage regulator low-power operation enable bit 1 = on-chip regulator enters low-power operation when device enters sleep mode 0 = on-chip regulator continues to operate normally in sleep mode bit 6-1 unimplemented : read as ? 0 ? bit 0 swdten: software controlled watchdog timer enable bit (1) 1 = watchdog timer is on 0 = watchdog timer is off note 1: the regslp bit is automatically cleared when a low-voltage detect condition occurs. 2: this bit has no effect if the configuration bit, wdten, is enabled. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page rcon ipen ? cm ri to pd por bor 52 wdtcon regslp ? ? ? ? ? ?swdten 52 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the watchdog timer. intrc oscillator wdt wake-up from reset wdt wdt counter programmable postscaler 1:1 to 1:32,768 enable wdt wdtps3:wdtps0 swdten clrwdt 4 power-managed reset all device resets sleep intrc control 128 modes ? 2007 microchip technology inc. preliminary ds39774c-page 279 pic18f85j11 family 22.3 on-chip voltage regulator all of the pic18f85j11 family devices power their core digital logic at a nominal 2.5v. for designs that are required to operate at a higher typical voltage, such as 3.3v, all devices in the pic18f85j11 family incorporate an on-chip regulator that allows the device to run its core logic from v dd . the regulator is controlled by the envreg pin. tying v dd to the pin enables the regulator, which in turn, pro- vides power to the core from the other v dd pins. when the regulator is enabled, a low-esr filter capacitor must be connected to the v ddcore /v cap pin (figure 22-2). this helps to maintain the stability of the regulator. the recommended value for the filter capacitor is provided in section 25.3 ?dc characteristics: pic18f85j11 family (industrial)? . if envreg is tied to v ss , the regulator is disabled. in this case, separate power for the core logic at a nominal 2.5v must be supplied to the device on the v ddcore /v cap pin to run the i/o pins at higher voltage levels, typically 3.3v. alternatively, the v ddcore /v cap and v dd pins can be tied together to operate at a lower nominal voltage. refer to figure 22-2 for possible configurations. 22.3.1 voltage regulation and low-voltage detection when it is enabled, the on-chip regulator provides a constant voltage of 2.5v nominal to the digital core logic. the regulator can provide this level from a v dd of about 2.5v, all the way up to the device?s v ddmax . it does not have the capability to boost v dd levels below 2.5v. in order to prevent ?brown-out? conditions, the regulator enters tracking mode when the voltage drops too low for the regulator. in tracking mode, the regulator output follows v dd , with a typical voltage drop of 100 mv. the on-chip regulator includes a simple low-voltage detect (lvd) circuit. if v dd drops too low to maintain approximately 2.45v on v ddcore , the circuit sets the low-voltage detect interrupt flag, lvdif (pir2<2>), and clears the regslp (wdtcon<7>) bit if it was set. this can be used to generate an interrupt and put the application into a low-power operational mode or to trigger an orderly shutdown. low-voltage detection is only available when the regulator is enabled. figure 22-2: conne ctions for the on-chip regulator v dd envreg v ddcore /v cap v ss pic18f85j11 3.3v (1) 2.5v (1) v dd envreg v ddcore /v cap v ss pic18f85j11 c f 3.3v regulator enabled (envreg tied to v dd ): regulator disabled (envreg tied to ground): v dd envreg v ddcore /v cap v ss pic18f85j11 2.5v (1) regulator disabled (v dd tied to v ddcore ): note 1: these are typical operating voltages. refer to section 25.1 ?dc characteristics: supply voltage? for the full operating ranges of v dd and v ddcore . pic18f85j11 family ds39774c-page 280 preliminary ? 2007 microchip technology inc. 22.3.2 on-chip regulator and bor when the on-chip regulator is enabled, pic18f85j11 family devices also have a simple brown-out reset capability. if the voltage supplied to the regulator falls to a level that is inadequate to maintain a regulated output for full-speed operation, the regulator reset circuitry will generate a brown-out reset. this event is captured by the bor flag bit (rcon<0>). the operation of the brown-out reset is described in more detail in section 4.4 ?brown-out reset (bor)? and section 4.4.1 ?detecting bor? . 22.3.3 power-up requirements the on-chip regulator is designed to meet the power-up requirements for the device. if the application does not use the regulator, then strict power-up conditions must be adhered to. while powering up, v ddcore must never exceed v dd by 0.3 volts. 22.3.4 operation in sleep mode when enabled, the on-chip regulator always consumes a small incremental amount of current over i dd . this includes when the device is in sleep mode, even though the core digital logic does not require power. to provide additional savings in applications where power resources are critical, the regulator can be configured to automatically disable itself whenever the device goes into sleep mode. this feature is controlled by the regslp bit (wdtcon<7>). setting this bit disables the regulator in sleep mode and reduces its current consumption to a minimum. substantial sleep-mode power savings can be obtained by setting the regslp bit, but this will increase device wake-up time to ensure the regulator has enough time to stabilize. the regslp bit is cleared automatically by hardware when a low-voltage detect condition occurs. the regslp bit can be set again in software, which would keep the voltage regulator in low-power mode. this is not recommended, however, if any write operations to the flash will be performed. ? 2007 microchip technology inc. preliminary ds39774c-page 281 pic18f85j11 family 22.4 two-speed start-up the two-speed start-up feature helps to minimize the latency period, from oscillator start-up to code execu- tion, by allowing the microcontroller to use the intrc oscillator as a clock source until the primary clock source is available. it is enabled by setting the ieso configuration bit. two-speed start-up should be enabled only if the primary oscillator mode is hs or hspll (crystal-based) modes. since the ec and ecpll modes do not require an oscillator start-up timer delay, two-speed start-up should be disabled. when enabled, resets and wake-ups from sleep mode cause the device to configure itself to run from the inter- nal oscillator block as the clock source, following the time-out of the power-up timer, after a power-on reset is enabled. this allows almost immediate code execution while the primary oscillator starts and the ost is running. once the ost times out, the device automatically switches to pri_run mode. in all other power-managed modes, two-speed start-up is not used. the device will be clocked by the currently selected clock source until the primary clock source becomes available. the setting of the ieso bit is ignored. 22.4.1 special considerations for using two-speed start-up while using the intrc oscillator in two-speed start-up, the device still obeys the normal command sequences for entering power-managed modes, including serial sleep instructions (refer to section 3.1.4 ?multiple sleep commands? ). in practice, this means that user code can change the scs1:scs0 bit settings or issue sleep instructions before the ost times out. this would allow an applica- tion to briefly wake-up, perform routine ?housekeeping? tasks and return to sleep before the device starts to operate from the primary oscillator. user code can also check if the primary clock source is currently providing the device clocking by checking the status of the osts bit (osccon<3>). if the bit is set, the primary oscillator is providing the clock. otherwise, the internal oscillator block is providing the clock during wake-up from reset or sleep mode. figure 22-3: timing transition for two-speed start-up (intrc to hspll) q1 q3 q4 osc1 peripheral program pc pc + 2 intrc pll clock q1 pc + 6 q2 output q3 q4 q1 cpu clock pc + 4 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. wake from interrupt event t pll (1) 12 n-1n clock osts bit set transition t ost (1) pic18f85j11 family ds39774c-page 282 preliminary ? 2007 microchip technology inc. 22.5 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. the fscm function is enabled by setting the fcmen configuration bit. when fscm is enabled, the intrc oscillator runs at all times to monitor clocks to peripherals and provides a backup clock in the event of a clock failure. clock monitoring (shown in figure 22-4) is accomplished by creating a sample clock signal which is the intrc out- put divided by 64. this allows ample time between fscm sample clocks for a peripheral clock edge to occur. the peripheral device clock and the sample clock are presented as inputs to the clock monitor latch (cm). the cm is set on the falling edge of the device clock source but cleared on the rising edge of the sample clock. figure 22-4: fscm block diagram clock failure is tested for on the falling edge of the sample clock. if a sample clock falling edge occurs while cm is still set, a clock failure has been detected (figure 22-5). this causes the following: ? the fscm generates an oscillator fail interrupt by setting bit, oscfif (pir2<7>); ? the device clock source is switched to the internal oscillator block (osccon is not updated to show the current clock source ? this is the fail-safe condition); and ?the wdt is reset. during switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing sensitive applications. in these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. this can be done to attempt a partial recovery or execute a controlled shutdown. see section 3.1.4 ?multiple sleep commands? and section 22.4.1 ?special considerations for using two-speed start-up? for more details. the fscm will detect failures of the primary or secondary clock sources only. if the internal oscillator block fails, no failure would be detected, nor would any action be possible. 22.5.1 fscm and the watchdog timer both the fscm and the wdt are clocked by the intrc oscillator. since the wdt operates with a separate divider and counter, disabling the wdt has no effect on the operation of the intrc oscillator when the fscm is enabled. as already noted, the clock source is switched to the intrc clock when a clock failure is detected. this may mean a substantial change in the speed of code execu- tion. if the wdt is enabled with a small prescale value, a decrease in clock speed allows a wdt time-out to occur and a subsequent device reset. for this reason, fail-safe clock monitor events also reset the wdt and postscaler, allowing it to start timing from when execu- tion speed was changed and decreasing the likelihood of an erroneous time-out. if the interrupt is disabled, subsequent interrupts while in idle mode will cause the cpu to begin executing instructions while being clocked by the intrc source. peripheral intrc 64 s c q (32 s) 488 hz (2.048 ms) clock monitor latch (cm) (edge-triggered) clock failure detected source clock q ? 2007 microchip technology inc. preliminary ds39774c-page 283 pic18f85j11 family figure 22-5: fscm timing diagram 22.5.2 exiting fail-safe operation the fail-safe condition is terminated by either a device reset or by entering a power-managed mode. on reset, the controller starts the primary clock source specified in configuration register 2h (with any required start-up delays that are required for the oscil- lator mode, such as ost or pll timer). the intrc oscillator provides the device clock until the primary clock source becomes ready (similar to a two-speed start-up). the clock source is then switched to the primary clock (indicated by the osts bit in the osccon register becoming set). the fail-safe clock monitor then resumes monitoring the peripheral clock. the primary clock source may never become ready during start-up. in this case, operation is clocked by the intosc multiplexor. the osccon register will remain in its reset state until a power-managed mode is entered. 22.5.3 fscm interrupts in power-managed modes by entering a power-managed mode, the clock multiplexor selects the clock source selected by the osccon register. fail-safe clock monitoring of the power-managed clock source resumes in the power-managed mode. if an oscillator failure occurs during power-managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. if enabled (oscfif = 1 ), code execution will be clocked by the intrc multiplexor. an automatic transition back to the failed clock source will not occur. 22.5.4 por or wake-up from sleep the fscm is designed to detect oscillator failure at any point after the device has exited power-on reset (por) or low-power sleep mode. when the primary device clock is either ec or intrc mode, monitoring can begin immediately following these events. for hs or hspll modes, the situation is somewhat different. since the oscillator may require a start-up time considerably longer than the fscm sample clock time, a false clock failure may be detected. to prevent this, the internal oscillator block is automatically config- ured as the device clock and functions until the primary clock is stable (the ost and pll timers have timed out). this is identical to two-speed start-up mode. once the primary clock is stable, the intrc returns to its role as the fscm source. as noted in section 22.4.1 ?special considerations for using two-speed start-up? , it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. when the new power-managed mode is selected, the primary clock is disabled. oscfif cm output device clock output sample clock failure detected oscillator failure note: the device clock is normally at a much higher frequency than the sample clock. the relative frequencies in this example have been chosen for clarity. (q ) cm test cm test cm test note: the same logic that prevents false oscillator failure interrupts on por, or wake from sleep, will also prevent the detection of the oscillator?s failure to start at all following these events. this can be avoided by monitoring the osts bit and using a timing routine to determine if the oscillator is taking too long to start. even so, no oscillator failure interrupt will be flagged. pic18f85j11 family ds39774c-page 284 preliminary ? 2007 microchip technology inc. 22.6 program verification and code protection for all devices in the pic18f85j11 family of devices, the on-chip program memory space is treated as a single block. code protection for this block is controlled by one configuration bit, cp0. this bit inhibits external reads and writes to the program memory space. it has no direct effect in normal execution mode. 22.6.1 configuration register protection the configuration registers are protected against untoward changes or reads in two ways. the primary protection is the write-once feature of the configuration bits which prevents reconfiguration once the bit has been programmed during a power cycle. to safeguard against unpredictable events, configuration bit changes resulting from individual cell level disruptions (such as esd events) will cause a parity error and trigger a device reset. the data for the configuration registers is derived from the flash configuration words in program memory. when the cp0 bit is set, the source data for device configuration is also protected as a consequence. 22.7 in-circuit serial programming pic18f85j11 family microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. 22.8 in-circuit debugger when the debug configuration bit is programmed to ? 0 ?, the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab ? ide. when the microcontroller has this feature enabled, some resources are not available for general use. table 22-4 shows which resources are required by the background debugger. table 22-4: debugger resources i/o pins: rb6, rb7 stack: 2 levels program memory: 512 bytes data memory: 10 bytes ? 2007 microchip technology inc. preliminary ds39774c-page 285 pic18f85j11 family 23.0 instruction set summary the pic18f85j11 family of devices incorporate the standard set of 75 pic18 core instructions, as well as an extended set of 8 new instructions for the optimiza- tion of code that is recursive or that utilizes a software stack. the extended set is discussed later in this section. 23.1 standard instruction set the standard pic18 instruction set adds many enhancements to the previous pic ? mcu instruction sets, while maintaining an easy migration from these pic mcu instruction sets. most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: ? byte-oriented operations ? bit-oriented operations ? literal operations ? control operations the pic18 instruction set summary in table 23-2 lists byte-oriented , bit-oriented , literal and control operations. table 23-1 shows the opcode field descriptions. most byte-oriented instructions have three operands: 1. the file select register (specified by ?f?). 2. the destination of the result (specified by ?d?). 3. the accessed memory (specified by ?a?). the file select register designator, ?f?, specifies which file select register is to be used by the instruction. the destination designator, ?d?, specifies where the result of the operation is to be placed. if ?d? is zero, the result is placed in the wreg register. if ?d? is one, the result is placed in the file select register specified in the instruction. all bit-oriented instructions have three operands: 1. the file select register (specified by ?f?). 2. the bit in the file select register (specified by ?b?). 3. the accessed memory (specified by ?a?). the bit field designator, ?b?, selects the number of the bit affected by the operation, while the file select register designator, ?f?, represents the number of the file in which the bit is located. the literal instructions may use some of the following operands: ? a literal value to be loaded into a file select register (specified by ?k?). ? the desired fsr register to load the literal value into (specified by ?f?). ? no operand required (specified by ???). the control instructions may use some of the following operands: ? a program memory address (specified by ?n?). ? the mode of the call or return instructions (specified by ?s?). ? the mode of the table read and table write instructions (specified by ?m?). ? no operand required (specified by ???). all instructions are a single word, except for four double-word instructions. these instructions were made double-word to contain the required information in 32 bits. in the second word, the 4 msbs are ? 1 ?s. if this second word is executed as an instruction (by itself), it will execute as a nop . all single-word instructions are executed in a single instruction cycle unless a conditional test is true or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a nop . the double-word instructions execute in two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. two-word branch instructions (if true) would take 3 s. figure 23-1 shows the general formats that the instruc- tions can have. all examples use the convention ?nnh? to represent a hexadecimal number. the instruction set summary, shown in table 23-2, lists the standard instructions recognized by the microchip mpasm tm assembler. section 23.1.1 ?standard instruction set? provides a description of each instruction. pic18f85j11 family ds39774c-page 286 preliminary ? 2007 microchip technology inc. table 23-1: opcode field descriptions field description a ram access bit: a = 0 : ram location in access ram (bsr register is ignored) a = 1 : ram bank is specified by bsr register bbb bit address within an 8-bit file select register (0 to 7). bsr bank select register. used to select the current ram bank. c, dc, z, ov, n alu status bits: c arry, d igit c arry, z ero, ov erflow, n egative. d destination select bit: d = 0 : store result in wreg d = 1 : store result in file select register f dest destination: either the wreg register or the specified register file location. f 8-bit register file address (00h to ff h) or 2-bit fsr designator (0h to 3h). f s 12-bit register file address (000h to fffh). this is the source address. f d 12-bit register file address (000h to ff fh). this is the destination address. gie global interrupt enable bit. k literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label label name. mm the mode of the tblptr register for the table read and table write instructions. only used with table read and table write instructions: * no change to register (such as tblptr with table reads and writes) *+ post-increment register (such as tblptr with table reads and writes) *- post-decrement register (such as tblptr with table reads and writes) +* pre-increment register (such as tb lptr with table reads and writes) n the relative address (2?s complement number) for relative branch instructions or the direct address for call/branch and return instructions. pc program counter. pcl program counter low byte. pch program counter high byte. pclath program counter high byte latch. pclatu program counter upper byte latch. pd power-down bit. prodh product of multiply high byte. prodl product of multiply low byte. s fast call/return mode select bit: s = 0 : do not update into/from shadow registers s = 1 : certain registers loaded into/from shadow registers (fast mode) tblptr 21-bit table pointer (points to a program memory location). tablat 8-bit table latch. to time-out bit. tos top-of-stack. u unused or unchanged. wdt watchdog timer. wreg working register (accumulator). x don?t care (? 0 ? or ? 1 ?). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. z s 7-bit offset value for indirect addressing of register files (source). z d 7-bit offset value for indirect addressing of register files (destination). { } optional argument. [text] indicates an indexed address. (text) the contents of text . [expr] ? 2007 microchip technology inc. preliminary ds39774c-page 287 pic18f85j11 family figure 23-1: general format for instructions byte-oriented file select register operations 15 10 9 8 7 0 d = 0 for result destination to be wreg register opcode d a f (file #) d = 1 for result destination to be file select register (f) a = 0 to force access bank bit-oriented file select register operations 15 12 11 9 8 7 0 opcode b (bit #) a f (file #) b = 3-bit position of bit in file select register (f) literal operations 15 8 7 0 opcode k (literal) k = 8-bit immediate value byte to byte move operations (2-word) 15 12 11 0 opcode f (source file #) call , goto and branch operations 15 8 7 0 opcode n<7:0> (literal) n = 20-bit immediate value a = 1 for bsr to select bank f = 8-bit file select register address a = 0 to force access bank a = 1 for bsr to select bank f = 8-bit file select register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (destination file #) f = 12-bit file select register address control operations example instruction addwf myreg, w, b movff myreg1, myreg2 bsf myreg, bit, b movlw 7fh goto label 15 8 7 0 opcode s n<7:0> (literal) 15 12 11 0 1111 n<19:8> (literal) call myfunc 15 11 10 0 opcode n<10:0> (literal) s = fast bit bra myfunc 15 8 7 0 opcode n<7:0> (literal) bc myfunc pic18f85j11 family ds39774c-page 288 preliminary ? 2007 microchip technology inc. table 23-2: pic18f85j11 family instruction set mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb byte-oriented operations addwf addwfc andwf clrf comf cpfseq cpfsgt cpfslt decf decfsz dcfsnz incf incfsz infsnz iorwf movf movff movwf mulwf negf rlcf rlncf rrcf rrncf setf subfwb subwf subwfb swapf tstfsz xorwf f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s , f d f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a add wreg and f add wreg and carry bit to f and wreg with f clear f complement f compare f with wreg, skip = compare f with wreg, skip > compare f with wreg, skip < decrement f decrement f, skip if 0 decrement f, skip if not 0 increment f increment f, skip if 0 increment f, skip if not 0 inclusive or wreg with f move f move f s (source) to 1st word f d (destination) 2nd word move wreg to f multiply wreg with f negate f rotate left f through carry rotate left f (no carry) rotate right f through carry rotate right f (no carry) set f subtract f from wreg with borrow subtract wreg from f subtract wreg from f with borrow swap nibbles in f test f, skip if 0 exclusive or wreg with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z, ov, n c, dc, z, ov, n z, n z z, n none none none c, dc, z, ov, n none none c, dc, z, ov, n none none z, n z, n none none none c, dc, z, ov, n c, z, n z, n c, z, n z, n none c, dc, z, ov, n c, dc, z, ov, n c, dc, z, ov, n none none z, n 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1, 2 1, 2 1, 2 1, 2 4 1, 2 note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if the program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. ? 2007 microchip technology inc. preliminary ds39774c-page 289 pic18f85j11 family bit-oriented operations bcf bsf btfsc btfss btg f, b, a f, b, a f, b, a f, b, a f, b, a bit clear f bit set f bit test f, skip if clear bit test f, skip if set bit toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff none none none none none 1, 2 1, 2 3, 4 3, 4 1, 2 control operations bc bn bnc bnn bnov bnz bov bra bz call clrwdt daw goto nop nop pop push rcall reset retfie retlw return sleep n n n n n n n n n n, s ? ? n ? ? ? ? n s k s ? branch if carry branch if negative branch if not carry branch if not negative branch if not overflow branch if not zero branch if overflow branch unconditionally branch if zero call subroutine 1st word 2nd word clear watchdog timer decimal adjust wreg go to address 1st word 2nd word no operation no operation pop top of return stack (tos) push top of return stack (tos) relative call software device reset return from interrupt enable return with literal in wreg return from subroutine go into standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 none none none none none none none none none none to , pd c none none none none none none all gie/gieh, peie/giel none none to , pd 4 table 23-2: pic18f85j11 family instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if the program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. pic18f85j11 family ds39774c-page 290 preliminary ? 2007 microchip technology inc. literal operations addlw andlw iorlw lfsr movlb movlw mullw retlw sublw xorlw k k k f, k k k k k k k add literal and wreg and literal with wreg inclusive or literal with wreg move literal (12-bit) 2nd word to fsr(f) 1st word move literal to bsr<3:0> move literal to wreg multiply literal with wreg return with literal in wreg subtract wreg from literal exclusive or literal with wreg 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z, ov, n z, n z, n none none none none none c, dc, z, ov, n z, n data memory ? program memory operations tblrd* tblrd*+ tblrd*- tblrd+* tblwt* tblwt*+ tblwt*- tblwt+* table read table read with post-increment table read with post-decrement table read with pre-increment table write table write with post-increment table write with post-decrement table write with pre-increment 2 2 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 none none none none none none none none table 23-2: pic18f85j11 family instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if the program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. ? 2007 microchip technology inc. preliminary ds39774c-page 291 pic18f85j11 family 23.1.1 standard instruction set addlw add literal to w syntax: addlw k operands: 0 k 255 operation: (w) + k w status affected: n, ov, c, dc, z encoding: 0000 1111 kkkk kkkk description: the contents of w are added to the 8-bit literal ?k? and the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: addlw 15h before instruction w = 10h after instruction w = 25h addwf add w to f syntax: addwf f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (w) + (f) dest status affected: n, ov, c, dc, z encoding: 0010 01da ffff ffff description: add w to register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: addwf reg, 0, 0 before instruction w = 17h reg = 0c2h after instruction w = 0d9h reg = 0c2h note: all pic18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. if a label is used, the instruction format then becomes: {label} instruction argument(s). pic18f85j11 family ds39774c-page 292 preliminary ? 2007 microchip technology inc. addwfc add w and carry bit to f syntax: addwfc f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (w) + (f) + (c) dest status affected: n, ov, c, dc, z encoding: 0010 00da ffff ffff description: add w, the carry flag and data memory location ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in data memory location ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: addwfc reg, 0, 1 before instruction carry bit = 1 reg = 02h w=4dh after instruction carry bit = 0 reg = 02h w = 50h andlw and literal with w syntax: andlw k operands: 0 k 255 operation: (w) .and. k w status affected: n, z encoding: 0000 1011 kkkk kkkk description: the contents of w are anded with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: andlw 05fh before instruction w=a3h after instruction w = 03h ? 2007 microchip technology inc. preliminary ds39774c-page 293 pic18f85j11 family andwf and w with f syntax: andwf f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (w) .and. (f) dest status affected: n, z encoding: 0001 01da ffff ffff description: the contents of w are anded with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: andwf reg, 0, 0 before instruction w = 17h reg = c2h after instruction w = 02h reg = c2h bc branch if carry syntax: bc n operands: -128 n 127 operation: if carry bit is ? 1 ?, (pc) + 2 + 2n pc status affected: none encoding: 1110 0010 nnnn nnnn description: if the carry bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bc 5 before instruction pc = address (here) after instruction if carry = 1 ; pc = address (here + 12) if carry = 0 ; pc = address (here + 2) pic18f85j11 family ds39774c-page 294 preliminary ? 2007 microchip technology inc. bcf bit clear f syntax: bcf f, b {,a} operands: 0 f 255 0 b 7 a [0, 1] operation: 0 f status affected: none encoding: 1001 bbba ffff ffff description: bit ?b? in register ?f? is cleared. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: bcf flag_reg, 7, 0 before instruction flag_reg = c7h after instruction flag_reg = 47h bn branch if negative syntax: bn n operands: -128 n 127 operation: if negative bit is ? 1 ?, (pc) + 2 + 2n pc status affected: none encoding: 1110 0110 nnnn nnnn description: if the negative bit is ? 1 ?, then the program will branch. the 2?s complement number, ?2n?, is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bn jump before instruction pc = address (here) after instruction if negative = 1 ; pc = address (jump) if negative = 0 ; pc = address (here + 2) ? 2007 microchip technology inc. preliminary ds39774c-page 295 pic18f85j11 family bnc branch if not carry syntax: bnc n operands: -128 n 127 operation: if carry bit is ? 0 ?, (pc) + 2 + 2n pc status affected: none encoding: 1110 0011 nnnn nnnn description: if the carry bit is ? 0 ?, then the program will branch. the 2?s complement number, ?2n?, is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnc jump before instruction pc = address (here) after instruction if carry = 0 ; pc = address (jump) if carry = 1 ; pc = address (here + 2) bnn branch if not negative syntax: bnn n operands: -128 n 127 operation: if negative bit is ? 0 ?, (pc) + 2 + 2n pc status affected: none encoding: 1110 0111 nnnn nnnn description: if the negative bit is ? 0 ?, then the program will branch. the 2?s complement number, ?2n?, is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnn jump before instruction pc = address (here) after instruction if negative = 0 ; pc = address (jump) if negative = 1 ; pc = address (here + 2) pic18f85j11 family ds39774c-page 296 preliminary ? 2007 microchip technology inc. bnov branch if not overflow syntax: bnov n operands: -128 n 127 operation: if overflow bit is ? 0 ?, (pc) + 2 + 2n pc status affected: none encoding: 1110 0101 nnnn nnnn description: if the overflow bit is ? 0 ?, then the program will branch. the 2?s complement number, ?2n?, is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnov jump before instruction pc = address (here) after instruction if overflow = 0 ; pc = address (jump) if overflow = 1 ; pc = address (here + 2) bnz branch if not zero syntax: bnz n operands: -128 n 127 operation: if zero bit is ? 0 ?, (pc) + 2 + 2n pc status affected: none encoding: 1110 0001 nnnn nnnn description: if the zero bit is ? 0 ?, then the program will branch. the 2?s complement number, ?2n?, is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnz jump before instruction pc = address (here) after instruction if zero = 0 ; pc = address (jump) if zero = 1 ; pc = address (here + 2) ? 2007 microchip technology inc. preliminary ds39774c-page 297 pic18f85j11 family bra unconditional branch syntax: bra n operands: -1024 n 1023 operation: (pc) + 2 + 2n pc status affected: none encoding: 1101 0nnn nnnn nnnn description: add the 2?s complement number, ?2n?, to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation example: here bra jump before instruction pc = address (here) after instruction pc = address (jump) bsf bit set f syntax: bsf f, b {,a} operands: 0 f 255 0 b 7 a [0, 1] operation: 1 f status affected: none encoding: 1000 bbba ffff ffff description: bit ?b? in register ?f? is set. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: bsf flag_reg, 7, 1 before instruction flag_reg = 0ah after instruction flag_reg = 8ah pic18f85j11 family ds39774c-page 298 preliminary ? 2007 microchip technology inc. btfsc bit test file, skip if clear syntax: btfsc f, b {,a} operands: 0 f 255 0 b 7 a [0, 1] operation: skip if (f) = 0 status affected: none encoding: 1011 bbba ffff ffff description: if bit ?b? in register ?f? is ? 0 ?, then the next instruction is skipped. if bit ?b? is ? 0 ?, then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here false true btfsc : : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0 ; pc = address (true) if flag<1> = 1 ; pc = address (false) btfss bit test file, skip if set syntax: btfss f, b {,a} operands: 0 f 255 0 b < 7 a [0, 1] operation: skip if (f) = 1 status affected: none encoding: 1010 bbba ffff ffff description: if bit ?b? in register ?f? is ? 1 ?, then the next instruction is skipped. if bit ?b? is ? 1 ?, then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here false true btfss : : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0 ; pc = address (false) if flag<1> = 1 ; pc = address (true) ? 2007 microchip technology inc. preliminary ds39774c-page 299 pic18f85j11 family btg bit toggle f syntax: btg f, b {,a} operands: 0 f 255 0 b < 7 a [0, 1] operation: (f ) f status affected: none encoding: 0111 bbba ffff ffff description: bit ?b? in data memory location ?f? is inverted. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: btg portc, 4, 0 before instruction: portc = 0111 0101 [75h] after instruction: portc = 0110 0101 [65h] bov branch if overflow syntax: bov n operands: -128 n 127 operation: if overflow bit is ? 1 ?, (pc) + 2 + 2n pc status affected: none encoding: 1110 0100 nnnn nnnn description: if the overflow bit is ? 1 ?, then the program will branch. the 2?s complement number, ?2n?, is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bov jump before instruction pc = address (here) after instruction if overflow = 1 ; pc = address (jump) if overflow = 0 ; pc = address (here + 2) pic18f85j11 family ds39774c-page 300 preliminary ? 2007 microchip technology inc. bz branch if zero syntax: bz n operands: -128 n 127 operation: if zero bit is ? 1 ?, (pc) + 2 + 2n pc status affected: none encoding: 1110 0000 nnnn nnnn description: if the zero bit is ? 1 ?, then the program will branch. the 2?s complement number, ?2n?, is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bz jump before instruction pc = address (here) after instruction if zero = 1 ; pc = address (jump) if zero = 0 ; pc = address (here + 2) call subroutine call syntax: call k {,s} operands: 0 k 1048575 s [0, 1] operation: (pc) + 4 tos, k pc<20:1>; if s = 1 , (w) ws, (status) statuss, (bsr) bsrs status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: subroutine call of entire 2-mbyte memory range. first, return address (pc+ 4) is pushed onto the return stack. if ?s? = 1 , the w, status and bsr registers are also pushed into their respective shadow registers, ws, statuss and bsrs. if ?s? = 0 , no update occurs (default). then, the 20-bit value, ?k?, is loaded into pc<20:1>. call is a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0>, push pc to stack read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example: here call there,1 before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 4) ws = w bsrs = bsr statuss = status ? 2007 microchip technology inc. preliminary ds39774c-page 301 pic18f85j11 family clrf clear f syntax: clrf f {,a} operands: 0 f 255 a [0, 1] operation: 000h f, 1 z status affected: z encoding: 0110 101a ffff ffff description: clears the contents of the specified register. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: clrf flag_reg,1 before instruction flag_reg = 5ah after instruction flag_reg = 00h clrwdt clear watchdog timer syntax: clrwdt operands: none operation: 000h wdt, 000h wdt postscaler, 1 to , 1 pd status affected: to , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watchdog timer. it also resets the postscaler of the wdt. status bits, to and pd , are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data no operation example: clrwdt before instruction wdt counter = ? after instruction wdt counter = 00h wdt postscaler = 0 to = 1 pd = 1 pic18f85j11 family ds39774c-page 302 preliminary ? 2007 microchip technology inc. comf complement f syntax: comf f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: f dest status affected: n, z encoding: 0001 11da ffff ffff description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: comf reg, 0, 0 before instruction reg = 13h after instruction reg = 13h w=ech cpfseq compare f with w, skip if f = w syntax: cpfseq f {,a} operands: 0 f 255 a [0, 1] operation: (f) ? (w), skip if (f) = (w) (unsigned comparison) status affected: none encoding: 0110 001a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if ?f? = w , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfseq reg, 0 nequal : equal : before instruction pc address = here w=? reg = ? after instruction if reg = w; pc = address (equal) if reg w; pc = address (nequal) ? 2007 microchip technology inc. preliminary ds39774c-page 303 pic18f85j11 family cpfsgt compare f with w, skip if f > w syntax: cpfsgt f {,a} operands: 0 f 255 a [0, 1] operation: (f) ? ( w), skip if (f) > (w) (unsigned comparison) status affected: none encoding: 0110 010a ffff ffff description: compares the contents of data memory location ?f? to the contents of the w by performing an unsigned subtraction. if the contents of ?f? are greater than the contents of wreg , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfsgt reg, 0 ngreater : greater : before instruction pc = address (here) w= ? after instruction if reg > w; pc = address (greater) if reg w; pc = address (ngreater) cpfslt compare f with w, skip if f < w syntax: cpfslt f {,a} operands: 0 f 255 a [0, 1] operation: (f) ? ( w), skip if (f) < (w) (unsigned comparison) status affected: none encoding: 0110 000a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if the contents of ?f? are less than the contents of w, then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfslt reg, 1 nless : less : before instruction pc = address (here) w= ? after instruction if reg < w; pc = address (less) if reg w; pc = address (nless) pic18f85j11 family ds39774c-page 304 preliminary ? 2007 microchip technology inc. daw decimal adjust w register syntax: daw operands: none operation: if [w<3:0> > 9] or [dc = 1 ], then (w<3:0>) + 6 w<3:0>; else (w<3:0>) w<3:0> if [w<7:4> > 9] or [c = 1 ], then (w<7:4>) + 6 w<7:4>; c = 1 ; else (w<7:4>) w<7:4> status affected: c encoding: 0000 0000 0000 0111 description: daw adjusts the eight-bit value in w, resulting from the earlier addition of two variables (each in packed bcd format) and produces a correct packed bcd result. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register w process data write w example 1: daw before instruction w=a5h c= 0 dc = 0 after instruction w = 05h c= 1 dc = 0 example 2: before instruction w=ceh c= 0 dc = 0 after instruction w = 34h c= 1 dc = 0 decf decrement f syntax: decf f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (f) ? 1 dest status affected: c, dc, n, ov, z encoding: 0000 01da ffff ffff description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: decf cnt, 1, 0 before instruction cnt = 01h z= 0 after instruction cnt = 00h z= 1 ? 2007 microchip technology inc. preliminary ds39774c-page 305 pic18f85j11 family decfsz decrement f, skip if 0 syntax: decfsz f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (f) ? 1 dest, skip if result = 0 status affected: none encoding: 0010 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here decfsz cnt, 1, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt ? 1 if cnt = 0 ; pc = address (continue) if cnt 0 ; pc = address (here + 2) dcfsnz decrement f, skip if not 0 syntax: dcfsnz f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (f) ? 1 dest, skip if result 0 status affected: none encoding: 0100 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is not ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here dcfsnz temp, 1, 0 zero : nzero : before instruction temp = ? after instruction temp = temp ? 1 if temp = 0 ; pc = address (zero) if temp 0 ; pc = address (nzero) pic18f85j11 family ds39774c-page 306 preliminary ? 2007 microchip technology inc. goto unconditional branch syntax: goto k operands: 0 k 1048575 operation: k pc<20:1> status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: goto allows an unconditional branch anywhere within entire 2-mbyte memory range. the 20-bit value, ?k?, is loaded into pc<20:1>. goto is always a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0>, no operation read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example: goto there after instruction pc = address (there) incf increment f syntax: incf f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (f) + 1 dest status affected: c, dc, n, ov, z encoding: 0010 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: incf cnt, 1, 0 before instruction cnt = ffh z= 0 c=? dc = ? after instruction cnt = 00h z= 1 c= 1 dc = 1 ? 2007 microchip technology inc. preliminary ds39774c-page 307 pic18f85j11 family incfsz increment f, skip if 0 syntax: incfsz f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (f) + 1 dest, skip if result = 0 status affected: none encoding: 0011 11da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f?. (default) if the result is ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here incfsz cnt, 1, 0 nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0 ; pc = address (zero) if cnt 0 ; pc = address (nzero) infsnz increment f, skip if not 0 syntax: infsnz f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (f) + 1 dest, skip if result 0 status affected: none encoding: 0100 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is not ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here infsnz reg, 1, 0 zero nzero before instruction pc = address (here) after instruction reg = reg + 1 if reg 0 ; pc = address (nzero) if reg = 0 ; pc = address (zero) pic18f85j11 family ds39774c-page 308 preliminary ? 2007 microchip technology inc. iorlw inclusive or literal with w syntax: iorlw k operands: 0 k 255 operation: (w) .or. k w status affected: n, z encoding: 0000 1001 kkkk kkkk description: the contents of w are ored with the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: iorlw 35h before instruction w=9ah after instruction w=bfh iorwf inclusive or w with f syntax: iorwf f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (w) .or. (f) dest status affected: n, z encoding: 0001 00da ffff ffff description: inclusive or w with register ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: iorwf result, 0, 1 before instruction result = 13h w = 91h after instruction result = 13h w = 93h ? 2007 microchip technology inc. preliminary ds39774c-page 309 pic18f85j11 family lfsr load fsr syntax: lfsr f, k operands: 0 f 2 0 k 4095 operation: k fsrf status affected: none encoding: 1110 1111 1110 0000 00ff k 7 kkk k 11 kkk kkkk description: the 12-bit literal ?k? is loaded into the file select register pointed to by ?f?. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? msb process data write literal ?k? msb to fsrfh decode read literal ?k? lsb process data write literal ?k? to fsrfl example: lfsr 2, 3abh after instruction fsr2h = 03h fsr2l = abh movf move f syntax: movf f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: f dest status affected: n, z encoding: 0101 00da ffff ffff description: the contents of register ?f? are moved to a destination dependent upon the status of ?d?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). location ?f? can be anywhere in the 256-byte bank. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write w example: movf reg, 0, 0 before instruction reg = 22h w=ffh after instruction reg = 22h w = 22h pic18f85j11 family ds39774c-page 310 preliminary ? 2007 microchip technology inc. movff move f to f syntax: movff f s ,f d operands: 0 f s 4095 0 f d 4095 operation: (f s ) f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1100 1111 ffff ffff ffff ffff ffff s ffff d description: the contents of source register, ?f s ?, are moved to destination register, ?f d ?. location of source, ?f s ?, can be anywhere in the 4096-byte data space (000h to fffh) and location of destination, ?f d ?, can also be anywhere from 000h to fffh. either source or destination can be w (a useful special situation). movff is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an i/o port). the movff instruction cannot use the pcl, tosu, tosh or tosl as the destination register words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read register ?f? (src) process data no operation decode no operation no dummy read no operation write register ?f? (dest) example: movff reg1, reg2 before instruction reg1 = 33h reg2 = 11h after instruction reg1 = 33h reg2 = 33h movlb move literal to low nibble in bsr syntax: movlw k operands: 0 k 255 operation: k bsr status affected: none encoding: 0000 0001 kkkk kkkk description: the eight-bit literal ?k? is loaded into the bank select register (bsr). the value of bsr<7:4> always remains ? 0 ? regardless of the value of k 7 :k 4 . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write literal ?k? to bsr example: movlb 5 before instruction bsr register = 02h after instruction bsr register = 05h ? 2007 microchip technology inc. preliminary ds39774c-page 311 pic18f85j11 family movlw move literal to w syntax: movlw k operands: 0 k 255 operation: k w status affected: none encoding: 0000 1110 kkkk kkkk description: the eight-bit literal ?k? is loaded into w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: movlw 5ah after instruction w=5ah movwf move w to f syntax: movwf f {,a} operands: 0 f 255 a [0, 1] operation: (w) f status affected: none encoding: 0110 111a ffff ffff description: move data from w to register ?f?. location ?f? can be anywhere in the 256-byte bank. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: movwf reg, 0 before instruction w=4fh reg = ffh after instruction w=4fh reg = 4fh pic18f85j11 family ds39774c-page 312 preliminary ? 2007 microchip technology inc. mullw multiply literal with w syntax: mullw k operands: 0 k 255 operation: (w) x k prodh:prodl status affected: none encoding: 0000 1101 kkkk kkkk description: an unsigned multiplication is carried out between the contents of w and the 8-bit literal ?k?. the 16-bit result is placed in the prodh:prodl register pair. prodh contains the high byte. w is unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write registers prodh: prodl example: mullw 0c4h before instruction w=e2h prodh = ? prodl = ? after instruction w=e2h prodh = adh prodl = 08h mulwf multiply w with f syntax: mulwf f {,a} operands: 0 f 255 a [0, 1] operation: (w) x (f) prodh:prodl status affected: none encoding: 0000 001a ffff ffff description: an unsigned multiplication is carried out between the contents of w and the register file location, ?f?. the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both w and ?f? are unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write registers prodh: prodl example: mulwf reg, 1 before instruction w=c4h reg = b5h prodh = ? prodl = ? after instruction w=c4h reg = b5h prodh = 8ah prodl = 94h ? 2007 microchip technology inc. preliminary ds39774c-page 313 pic18f85j11 family negf negate f syntax: negf f {,a} operands: 0 f 255 a [0, 1] operation: (f ) + 1 f status affected: n, ov, c, dc, z encoding: 0110 110a ffff ffff description: location ?f? is negated using two?s complement. the result is placed in the data memory location ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: negf reg, 1 before instruction reg = 0011 1010 [3ah] after instruction reg = 1100 0110 [c6h] nop no operation syntax: nop operands: none operation: no operation status affected: none encoding: 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example: none. pic18f85j11 family ds39774c-page 314 preliminary ? 2007 microchip technology inc. pop pop top of return stack syntax: pop operands: none operation: (tos) bit bucket status affected: none encoding: 0000 0000 0000 0110 description: the tos value is pulled off the return stack and is discarded. the tos value then becomes the previous value that was pushed onto the return stack. this instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation pop tos value no operation example: pop goto new before instruction tos = 0031a2h stack (1 level down) = 014332h after instruction tos = 014332h pc = new push push top of return stack syntax: push operands: none operation: (pc + 2) tos status affected: none encoding: 0000 0000 0000 0101 description: the pc + 2 is pushed onto the top of the return stack. the previous tos value is pushed down on the stack. this instruction allows implementing a software stack by modifying tos and then pushing it onto the return stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode push pc + 2 onto return stack no operation no operation example: push before instruction tos = 345ah pc = 0124h after instruction pc = 0126h tos = 0126h stack (1 level down) = 345ah ? 2007 microchip technology inc. preliminary ds39774c-page 315 pic18f85j11 family rcall relative call syntax: rcall n operands: -1024 n 1023 operation: (pc) + 2 tos, (pc) + 2 + 2n pc status affected: none encoding: 1101 1nnn nnnn nnnn description: subroutine call with a jump up to 1k from the current location. first, return address (pc + 2) is pushed onto the stack. then, add the 2?s complement number, ?2n?, to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? push pc to stack process data write to pc no operation no operation no operation no operation example: here rcall jump before instruction pc = address (here) after instruction pc = address (jump) tos = address (here + 2) reset reset syntax: reset operands: none operation: reset all registers and flags that are affected by a mclr reset. status affected: all encoding: 0000 0000 1111 1111 description: this instruction provides a way to execute a mclr reset in software. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode start reset no operation no operation example: reset after instruction registers = reset value flags* = reset value pic18f85j11 family ds39774c-page 316 preliminary ? 2007 microchip technology inc. retfie return from interrupt syntax: retfie {s} operands: s [0, 1] operation: (tos) pc, 1 gie/gieh or peie/giel; if s = 1 , (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged status affected: gie/gieh, peie/giel. encoding: 0000 0000 0001 000s description: return from interrupt. stack is popped and top-of-stack (tos) is loaded into the pc. interrupts are enabled by setting either the high or low priority global interrupt enable bit. if ?s? = 1 , the contents of the shadow registers, ws, statuss and bsrs, are loaded into their corresponding registers, w, status and bsr. if ?s? = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation pop pc from stack set gieh or giel no operation no operation no operation no operation example: retfie 1 after interrupt pc = tos w=ws bsr = bsrs status = statuss gie/gieh, peie/giel = 1 retlw return literal to w syntax: retlw k operands: 0 k 255 operation: k w, (tos) pc, pclatu, pclath are unchanged status affected: none encoding: 0000 1100 kkkk kkkk description: w is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data pop pc from stack, write to w no operation no operation no operation no operation example: call table ; w contains table ; offset value ; w now has ; table value : table addwf pcl ; w = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction w = 07h after instruction w = value of kn ? 2007 microchip technology inc. preliminary ds39774c-page 317 pic18f85j11 family return return from subroutine syntax: return {s} operands: s [0, 1] operation: (tos) pc; if s = 1 , (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged status affected: none encoding: 0000 0000 0001 001s description: return from subroutine. the stack is popped and the top of the stack (tos) is loaded into the program counter. if ?s?= 1 , the contents of the shadow registers, ws, statuss and bsrs, are loaded into their corresponding registers, w, status and bsr. if ?s? = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation process data pop pc from stack no operation no operation no operation no operation example: return after instruction: pc = tos rlcf rotate left f through carry syntax: rlcf f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (f pic18f85j11 family ds39774c-page 318 preliminary ? 2007 microchip technology inc. rlncf rotate left f (no carry) syntax: rlncf f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (f ? 2007 microchip technology inc. preliminary ds39774c-page 319 pic18f85j11 family rrncf rotate right f (no carry) syntax: rrncf f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (f pic18f85j11 family ds39774c-page 320 preliminary ? 2007 microchip technology inc. sleep enter sleep mode syntax: sleep operands: none operation: 00h wdt, 0 wdt postscaler, 1 to , 0 pd status affected: to , pd encoding: 0000 0000 0000 0011 description: the power-down status bit (pd ) is cleared. the time-out status bit (to ) is set. the watchdog timer and its postscaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data go to sleep example: sleep before instruction to =? pd =? after instruction to = 1 ? pd = 0 ? if wdt causes wake-up, this bit is cleared. subfwb subtract f from w with borrow syntax: subfwb f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (w) ? (f) ? (c ) dest status affected: n, ov, c, dc, z encoding: 0101 01da ffff ffff description: subtract register ?f? and carry flag (borrow) from w (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subfwb reg, 1, 0 before instruction reg = 3 w=2 c=1 after instruction reg = ff w=2 c=0 z=0 n = 1 ; result is negative example 2: subfwb reg, 0, 0 before instruction reg = 2 w=5 c=1 after instruction reg = 2 w=3 c=1 z=0 n = 0 ; result is positive example 3: subfwb reg, 1, 0 before instruction reg = 1 w=2 c=0 after instruction reg = 0 w=2 c=1 z = 1 ; result is zero n=0 ? 2007 microchip technology inc. preliminary ds39774c-page 321 pic18f85j11 family sublw subtract w from literal syntax: sublw k operands: 0 k 255 operation: k ? (w) w status affected: n, ov, c, dc, z encoding: 0000 1000 kkkk kkkk description: w is subtracted from the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example 1: sublw 02h before instruction w = 01h c=? after instruction w = 01h c= 1 ; result is positive z= 0 n= 0 example 2: sublw 02h before instruction w = 02h c=? after instruction w = 00h c= 1 ; result is zero z= 1 n= 0 example 3: sublw 02h before instruction w = 03h c=? after instruction w = ffh ; (2?s complement) c= 0 ; result is negative z= 0 n= 1 subwf subtract w from f syntax: subwf f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (f) ? (w) dest status affected: n, ov, c, dc, z encoding: 0101 11da ffff ffff description: subtract w from register ?f? (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subwf reg, 1, 0 before instruction reg = 3 w=2 c=? after instruction reg = 1 w=2 c = 1 ; result is positive z=0 n=0 example 2: subwf reg, 0, 0 before instruction reg = 2 w=2 c=? after instruction reg = 2 w=0 c = 1 ; result is zero z=1 n=0 example 3: subwf reg, 1, 0 before instruction reg = 1 w=2 c=? after instruction reg = ffh ; (2?s complement) w=2 c = 0 ; result is negative z=0 n=1 pic18f85j11 family ds39774c-page 322 preliminary ? 2007 microchip technology inc. subwfb subtract w from f with borrow syntax: subwfb f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (f) ? (w) ? (c ) dest status affected: n, ov, c, dc, z encoding: 0101 10da ffff ffff description: subtract w and the carry flag (borrow) from register ?f? (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subwfb reg, 1, 0 before instruction reg = 19h (0001 1001) w=0dh (0000 1101) c= 1 after instruction reg = 0ch (0000 1011) w=0dh (0000 1101) c= 1 z= 0 n= 0 ; result is positive example 2: subwfb reg, 0, 0 before instruction reg = 1bh (0001 1011) w=1ah (0001 1010) c= 0 after instruction reg = 1bh (0001 1011) w = 00h c= 1 z= 1 ; result is zero n= 0 example 3: subwfb reg, 1, 0 before instruction reg = 03h (0000 0011) w=0eh (0000 1101) c= 1 after instruction reg = f5h (1111 0100) ; [2?s comp] w=0eh (0000 1101) c= 0 z= 0 n= 1 ; result is negative swapf swap f syntax: swapf f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> status affected: none encoding: 0011 10da ffff ffff description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: swapf reg, 1, 0 before instruction reg = 53h after instruction reg = 35h ? 2007 microchip technology inc. preliminary ds39774c-page 323 pic18f85j11 family tblrd table read syntax: tblrd ( *; *+; *-; +*) operands: none operation: if tblrd *, (prog mem (tblptr)) tablat; tblptr ? no change if tblrd *+, (prog mem (tblptr)) tablat; (tblptr) + 1 tblptr if tblrd *-, (prog mem (tblptr)) tablat; (tblptr) ? 1 tblptr if tblrd +*, (tblptr) + 1 tblptr; (prog mem (tblptr)) tablat status affected: none encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to read the contents of program memory (p.m.). to address the program memory, a pointer called table pointer (tblptr) is used. the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. tblptr<0> = 0 :least significant byte of program memory word tblptr<0> = 1 :most significant byte of program memory word the tblrd instruction can modify the value of tblptr as follows: ? no change ? post-increment ? post-decrement ? pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read program memory) no operation no operation (write tablat) tblrd table read (continued) example 1: tblrd *+ ; before instruction tablat = 55h tblptr = 00a356h memory(00a356h) = 34h after instruction tablat = 34h tblptr = 00a357h example 2: tblrd +* ; before instruction tablat = aah tblptr = 01a357h memory(01a357h) = 12h memory(01a358h) = 34h after instruction tablat = 34h tblptr = 01a358h pic18f85j11 family ds39774c-page 324 preliminary ? 2007 microchip technology inc. tblwt table write syntax: tblwt ( *; *+; *-; +*) operands: none operation: if tblwt*, (tablat) holding register; tblptr ? no change if tblwt*+, (tablat) holding register; (tblptr) + 1 tblptr if tblwt*-, (tablat) holding register; (tblptr) ? 1 tblptr if tblwt+*, (tblptr) + 1 tblptr; (tablat) holding register status affected: none encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction uses the 3 lsbs of tblptr to determine which of the 8 holding registers the tablat is written to. the holding registers are used to program the contents of program memory (p.m.). (refer to section 5.0 ?memory organization? for additional details on programming flash memory.) the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. the lsb of the tblptr selects which byte of the program memory location to access. tblptr<0> = 0 :least significant byte of program memory word tblptr<0> = 1 :most significant byte of program memory word the tblwt instruction can modify the value of tblptr as follows: ? no change ? post-increment ? post-decrement ? pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read tablat) no operation no operation (write to holding register) tblwt table write (continued) example 1: tblwt *+; before instruction tablat = 55h tblptr = 00a356h holding register (00a356h) = ffh after instructions (table write completion) tablat = 55h tblptr = 00a357h holding register (00a356h) = 55h example 2: tblwt +*; before instruction tablat = 34h tblptr = 01389ah holding register (01389ah) = ffh holding register (01389bh) = ffh after instruction (table write completion) tablat = 34h tblptr = 01389bh holding register (01389ah) = ffh holding register (01389bh) = 34h ? 2007 microchip technology inc. preliminary ds39774c-page 325 pic18f85j11 family tstfsz test f, skip if 0 syntax: tstfsz f {,a} operands: 0 f 255 a [0, 1] operation: skip if f = 0 status affected: none encoding: 0110 011a ffff ffff description: if ?f? = 0 , the next instruction fetched during the current instruction execution is discarded and a nop is executed, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here tstfsz cnt, 1 nzero : zero : before instruction pc = address (here) after instruction if cnt = 00h, pc = address (zero) if cnt 00h, pc = address (nzero) xorlw exclusive or literal with w syntax: xorlw k operands: 0 k 255 operation: (w) .xor. k w status affected: n, z encoding: 0000 1010 kkkk kkkk description: the contents of w are xored with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: xorlw 0afh before instruction w=b5h after instruction w=1ah pic18f85j11 family ds39774c-page 326 preliminary ? 2007 microchip technology inc. xorwf exclusive or w with f syntax: xorwf f {,d {,a}} operands: 0 f 255 d [0, 1] a [0, 1] operation: (w) .xor. (f) dest status affected: n, z encoding: 0001 10da ffff ffff description: exclusive or the contents of w with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in the register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 23.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: xorwf reg, 1, 0 before instruction reg = afh w=b5h after instruction reg = 1ah w=b5h ? 2007 microchip technology inc. preliminary ds39774c-page 327 pic18f85j11 family 23.2 extended instruction set in addition to the standard 75 instructions of the pic18 instruction set, the pic18f85j11 family of devices also provides an optional extension to the core cpu func- tionality. the added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of indexed literal offset addressing for many of the standard pic18 instructions. the additional features of the extended instruction set are enabled by default on unprogrammed devices. users must properly set or clear the xinst configura- tion bit during programming to enable or disable these features. the instructions in the extended set can all be classified as literal operations, which either manipulate the file select registers, or use them for indexed addressing. two of the instructions, addfsr and subfsr , each have an additional special instantiation for using fsr2. these versions ( addulnk and subulnk ) allow for automatic return after execution. the extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly c. among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. these include: ? dynamic allocation and deallocation of software stack space when entering and leaving subroutines ? function pointer invocation ? software stack pointer manipulation ? manipulation of variables located in a software stack a summary of the instructions in the extended instruc- tion set is provided in table 23-3. detailed descriptions are provided in section 23.2.2 ?extended instruction set? . the opcode field descriptions in table 23-1 (page 286) apply to both the standard and extended pic18 instruction sets. 23.2.1 extended instruction syntax most of the extended instructions use indexed argu- ments, using one of the file select registers and some offset to specify a source or destination register. when an argument for an instruction serves as part of indexed addressing, it is enclosed in square brackets (?[ ]?). this is done to indicate that the argument is used as an index or offset. the mpasm? assembler will flag an error if it determines that an index or offset value is not bracketed. when the extended instruction set is enabled, brackets are also used to indicate index arguments in byte-oriented and bit-oriented instructions. this is in addition to other changes in their syntax. for more details, see section 23.2.3.1 ?extended instruction syntax with standard pic18 commands? . table 23-3: extensions to the pic18 instruction set note: the instruction set extension and the indexed literal offset addressing mode were designed for optimizing applications written in c. the user may likely never use these instructions directly in the assem- bler. the syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler. note: in the past, square brackets have been used to denote optional arguments in the pic18 and earlier instruction sets. in this text, and going forward, optional arguments are denoted by braces (?{ }?). mnemonic, operands description cycles 16-bit instruction word status affected msb lsb addfsr addulnk callw movsf movss pushl subfsr subulnk f, k k z s , f d z s , z d k f, k k add literal to fsr add literal to fsr2 and return call subroutine using wreg move z s (source) to 1st word f d (destination) 2nd word move z s (source) to 1st word z d (destination) 2nd word store literal at fsr2, decrement fsr2 subtract literal from fsr subtract literal from fsr2 and return 1 2 2 2 2 1 1 2 1110 1110 0000 1110 1111 1110 1111 1110 1110 1110 1000 1000 0000 1011 ffff 1011 xxxx 1010 1001 1001 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk ffkk 11kk kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk kkkk kkkk none none none none none none none none pic18f85j11 family ds39774c-page 328 preliminary ? 2007 microchip technology inc. 23.2.2 extended instruction set addfsr add literal to fsr syntax: addfsr f, k operands: 0 k 63 f [ 0, 1, 2 ] operation: fsr(f) + k fsr(f) status affected: none encoding: 1110 1000 ffkk kkkk description: the 6-bit literal ?k? is added to the contents of the fsr specified by ?f?. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to fsr example: addfsr 2, 23h before instruction fsr2 = 03ffh after instruction fsr2 = 0422h addulnk add literal to fsr2 and return syntax: addulnk k operands: 0 k 63 operation: fsr2 + k fsr2, (tos) pc status affected: none encoding: 1110 1000 11kk kkkk description: the 6-bit literal ?k? is added to the contents of fsr2. a return is then executed by loading the pc with the tos. the instruction takes two cycles to execute; a nop is performed during the second cycle. this may be thought of as a special case of the addfsr instruction, where f = 3 (binary ? 11 ?); it operates only on fsr2. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to fsr no operation no operation no operation no operation example: addulnk 23h before instruction fsr2 = 03ffh pc = 0100h after instruction fsr2 = 0422h pc = (tos) note: all pic18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. if a label is used, the instruction format then becomes: {label} instruction argument(s). ? 2007 microchip technology inc. preliminary ds39774c-page 329 pic18f85j11 family callw subroutine call using wreg syntax: callw operands: none operation: (pc + 2) tos, (w) pcl, (pclath) pch, (pclatu) pcu status affected: none encoding: 0000 0000 0001 0100 description first, the return address (pc + 2) is pushed onto the return stack. next, the contents of w are written to pcl; the existing value is discarded. then, the contents of pclath and pclatu are latched into pch and pcu, respectively. the second cycle is executed as a nop instruction while the new next instruction is fetched. unlike call , there is no option to update w, status or bsr. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read wreg push pc to stack no operation no operation no operation no operation no operation example: here callw before instruction pc = address (here) pclath = 10h pclatu = 00h w = 06h after instruction pc = 001006h tos = address (here + 2) pclath = 10h pclatu = 00h w = 06h movsf move indexed to f syntax: movsf [z s ], f d operands: 0 z s 127 0 f d 4095 operation: ((fsr2) + z s ) f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1110 1111 1011 ffff 0zzz ffff zzzz s ffff d description: the contents of the source register are moved to destination register, ?f d ?. the actual address of the source register is determined by adding the 7-bit literal offset, ?z s ?, in the first word to the value of fsr2. the address of the destination register is specified by the 12-bit literal, ?f d ?, in the second word. both addresses can be anywhere in the 4096-byte data space (000h to fffh). the movsf instruction cannot use the pcl, tosu, tosh or tosl as the destination register. if the resultant source address points to an indirect addressing register, the value returned will be 00h. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode determine source addr determine source addr read source reg decode no operation no dummy read no operation write register ?f? (dest) example: movsf [05h], reg2 before instruction fsr2 = 80h contents of 85h = 33h reg2 = 11h after instruction fsr2 = 80h contents of 85h = 33h reg2 = 33h pic18f85j11 family ds39774c-page 330 preliminary ? 2007 microchip technology inc. movss move indexed to indexed syntax: movss [z s ], [z d ] operands: 0 z s 127 0 z d 127 operation: ((fsr2) + z s ) ((fsr2) + z d ) status affected: none encoding: 1st word (source) 2nd word (dest.) 1110 1111 1011 xxxx 1zzz xzzz zzzz s zzzz d description the contents of the source register are moved to the destination register. the addresses of the source and destination registers are determined by adding the 7-bit literal offsets, ?z s ? or ?z d ?, respectively, to the value of fsr2. both registers can be located anywhere in the 4096-byte data memory space (000h to fffh). the movss instruction cannot use the pcl, tosu, tosh or tosl as the destination register. if the resultant source address points to an indirect addressing register, the value returned will be 00h. if the resultant destination address points to an indirect addressing register, the instruction will execute as a nop . words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode determine source addr determine source addr read source reg decode determine dest addr determine dest addr write to dest reg example: movss [05h], [06h] before instruction fsr2 = 80h contents of 85h = 33h contents of 86h = 11h after instruction fsr2 = 80h contents of 85h = 33h contents of 86h = 33h pushl store literal at fsr2, decrement fsr2 syntax: pushl k operands: 0 k 255 operation: k (fsr2), fsr2 ? 1 fsr2 status affected: none encoding: 1111 1010 kkkk kkkk description: the 8-bit literal ?k? is written to the data memory address specified by fsr2. fsr2 is decremented by 1 after the operation. this instruction allows users to push values onto a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read ?k? process data write to destination example: pushl 08h before instruction fsr2h:fsr2l = 01ech memory (01ech) = 00h after instruction fsr2h:fsr2l = 01ebh memory (01ech) = 08h ? 2007 microchip technology inc. preliminary ds39774c-page 331 pic18f85j11 family subfsr subtract literal from fsr syntax: subfsr f, k operands: 0 k 63 f [ 0, 1, 2 ] operation: fsrf ? k fsrf status affected: none encoding: 1110 1001 ffkk kkkk description: the 6-bit literal, ?k?, is subtracted from the contents of the fsr specified by ?f?. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: subfsr 2, 23h before instruction fsr2 = 03ffh after instruction fsr2 = 03dch subulnk subtract literal from fsr2 and return syntax: subulnk k operands: 0 k 63 operation: fsr2 ? k fsr2, (tos) pc status affected: none encoding: 1110 1001 11kk kkkk description: the 6-bit literal, ?k?, is subtracted from the contents of the fsr2. a return is then executed by loading the pc with the tos. the instruction takes two cycles to execute; a nop is performed during the second cycle. this may be thought of as a special case of the subfsr instruction, where f = 3 (binary ? 11 ?); it operates only on fsr2. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination no operation no operation no operation no operation example: subulnk 23h before instruction fsr2 = 03ffh pc = 0100h after instruction fsr2 = 03dch pc = (tos) pic18f85j11 family ds39774c-page 332 preliminary ? 2007 microchip technology inc. 23.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode in addition to eight new commands in the extended set, enabling the extended instruction set also enables indexed literal offset addressing ( section 5.6.1 ?indexed addressing with literal offset? ). this has a significant impact on the way that many commands of the standard pic18 instruction set are interpreted. when the extended set is disabled, addresses embed- ded in opcodes are treated as literal memory locations: either as a location in the access bank (a = 0 ) or in a gpr bank designated by the bsr (a = 1 ). when the extended instruction set is enabled and a = 0 , however, a file select register argument of 5fh or less is inter- preted as an offset from the pointer value in fsr2 and not as a literal address. for practical purposes, this means that all instructions that use the access ram bit as an argument ? that is, all byte-oriented and bit-oriented instructions, or almost half of the core pic18 instructions ? may behave differently when the extended instruction set is enabled. when the content of fsr2 is 00h, the boundaries of the access ram are essentially remapped to their original values. this may be useful in creating backward-compatible code. if this technique is used, it may be necessary to save the value of fsr2 and restore it when moving back and forth between c and assembly routines in order to preserve the stack pointer. users must also keep in mind the syntax requirements of the extended instruction set (see section 23.2.3.1 ?extended instruction syntax with standard pic18 commands? ). although the indexed literal offset mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic opera- tion is carried out on the wrong register. users who are accustomed to the pic18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5fh or less are used for indexed literal offset addressing. representative examples of typical byte-oriented and bit-oriented instructions in the indexed literal offset mode are provided on the following page to show how execution is affected. the operand conditions shown in the examples are applicable to all instructions of these types. 23.2.3.1 extended instruction syntax with standard pic18 commands when the extended instruction set is enabled, the file select register argument, ?f?, in the standard, byte-oriented and bit-oriented commands is replaced with the literal offset value, ?k?. as already noted, this occurs only when ?f? is less than or equal to 5fh. when an offset value is used, it must be indicated by square brackets (?[ ]?). as with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. omitting the brackets, or using a value greater than 5fh within the brackets, will generate an error in the mpasm assembler. if the index argument is properly bracketed for indexed literal offset addressing, the access ram argument is never specified; it will automatically be assumed to be ? 0 ?. this is in contrast to standard operation (extended instruction set disabled) when ?a? is set on the basis of the target address. declaring the access ram bit in this mode will also generate an error in the mpasm assembler. the destination argument, ?d?, functions as before. in the latest versions of the mpasm assembler, language support for the extended instruction set must be explicitly invoked. this is done with either the command line option, /y , or the pe directive in the source listing. 23.2.4 considerations when enabling the extended instruction set it is important to note that the extensions to the instruc- tion set may not be beneficial to all users. in particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. additionally, the indexed literal offset addressing mode may create issues with legacy applications written to the pic18 assembler. this is because instructions in the legacy code may attempt to address registers in the access bank below 5fh. since these addresses are interpreted as literal offsets to fsr2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. when porting an application to the pic18f85j11 family, it is very important to consider the type of code. a large, re-entrant application that is written in c and would ben- efit from efficient compilation will do well when using the instruction set extensions. legacy applications that heavily use the access bank will most likely not benefit from using the extended instruction set. note: enabling the pic18 instruction set exten- sion may cause legacy applications to behave erratically or fail entirely. ? 2007 microchip technology inc. preliminary ds39774c-page 333 pic18f85j11 family addwf add w to indexed (indexed literal offset mode) syntax: addwf [k] {,d} operands: 0 k 95 d [0, 1] operation: (w) + ((fsr2) + k) dest status affected: n, ov, c, dc, z encoding: 0010 01d0 kkkk kkkk description: the contents of w are added to the contents of the register indicated by fsr2, offset by the value, ?k?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read ?k? process data write to destination example: addwf [ofst] ,0 before instruction w = 17h ofst = 2ch fsr2 = 0a00h contents of 0a2ch = 20h after instruction w = 37h contents of 0a2ch = 20h bsf bit set indexed (indexed literal offset mode) syntax: bsf [k], b operands: 0 f 95 0 b 7 operation: 1 ((fsr2) + k) status affected: none encoding: 1000 bbb0 kkkk kkkk description: bit ?b? of the register indicated by fsr2, offset by the value, ?k?, is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: bsf [flag_ofst], 7 before instruction flag_ofst = 0ah fsr2 = 0a00h contents of 0a0ah = 55h after instruction contents of 0a0ah = d5h setf set indexed (indexed literal offset mode) syntax: setf [k] operands: 0 k 95 operation: ffh ((fsr2) + k) status affected: none encoding: 0110 1000 kkkk kkkk description: the contents of the register indicated by fsr2, offset by ?k?, are set to ffh. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read ?k? process data write register example: setf [ofst] before instruction ofst = 2ch fsr2 = 0a00h contents of 0a2ch = 00h after instruction contents of 0a2ch = ffh pic18f85j11 family ds39774c-page 334 preliminary ? 2007 microchip technology inc. 23.2.5 special considerations with microchip mplab ? ide tools the latest versions of microchip?s software tools have been designed to fully support the extended instruction set for the pic18f85j11 family. this includes the mplab c18 c compiler, mpasm assembly language and mplab integrated development environment (ide). when selecting a target device for software development, mplab ide will automatically set default configuration bits for that device. the default setting for the xinst configuration bit is ? 0 ?, disabling the extended instruction set and indexed literal offset addressing. for proper execution of applications developed to take advantage of the extended instruction set, xinst must be set during programming. to develop software for the extended instruction set, the user must enable support for the instructions and the indexed addressing mode in their language tool(s). depending on the environment being used, this may be done in several ways: ? a menu option or dialog box within the environment that allows the user to configure the language tool and its settings for the project ? a command line option ? a directive in the source code these options vary between different compilers, assemblers and development environments. users are encouraged to review the documentation accompany- ing their development systems for the appropriate information. ? 2007 microchip technology inc. preliminary ds39774c-page 335 pic18f85j11 family 24.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c18 and mplab c30 c compilers -mplink tm object linker/ mplib tm object librarian - mplab asm30 assembler/linker/library ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - mplab real ice? in-circuit emulator ? in-circuit debugger - mplab icd 2 ? device programmers - picstart ? plus development programmer - mplab pm3 device programmer - pickit? 2 development programmer ? low-cost demonstration and development boards and evaluation kits 24.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? visual device initializer for easy register initialization ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as hi-tech software c compilers and iar c compilers the mplab ide allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to pic mcu emulator and simulator tools (automatically updates all project information) ? debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power. pic18f85j11 family ds39774c-page 336 preliminary ? 2007 microchip technology inc. 24.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all pic mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 24.3 mplab c18 and mplab c30 c compilers the mplab c18 and mplab c30 code development systems are complete ansi c compilers for microchip?s pic18 and pic24 families of microcontrol- lers and the dspic30 and dspic33 family of digital sig- nal controllers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 24.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 24.5 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire dspic30f instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility 24.6 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c18 and mplab c30 c compilers, and the mpasm and mplab asm30 assemblers. the software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. ? 2007 microchip technology inc. preliminary ds39774c-page 337 pic18f85j11 family 24.7 mplab ice 2000 high-performance in-circuit emulator the mplab ice 2000 in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator system with enhanced trace, trigger and data monitor- ing features. interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. the architecture of the mplab ice 2000 in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows ? 32-bit operating system were chosen to best make these features available in a simple, unified application. 24.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc ? and mcu devices. it debugs and programs pic ? and dspic ? flash microcontrollers with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the mplab real ice probe is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with the popular mplab icd 2 system (rj11) or with the new high speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). mplab real ice is field upgradeable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 24.9 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash pic mcus and can be used to develop for these and other pic mcus and dspic dscs. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost- effective, in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single step- ping and watching variables, and cpu status and peripheral registers. running at full speed enables testing hardware and applications in real time. mplab icd 2 also serves as a development programmer for selected pic devices. 24.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an sd/mmc card for file storage and secure data applications. pic18f85j11 family ds39774c-page 338 preliminary ? 2007 microchip technology inc. 24.11 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it connects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most pic devices in dip packages up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 24.12 pickit 2 development programmer the pickit? 2 development programmer is a low-cost programmer and selected flash device debugger with an easy-to-use interface for programming many of microchip?s baseline, mid-range and pic18f families of flash memory microcontrollers. the pickit 2 starter kit includes a prototyping development board, twelve sequential lessons, software and hi-tech?s picc? lite c compiler, and is designed to help get up to speed quickly using pic ? microcontrollers. the kit provides everything needed to program, evaluate and develop applications using microchip?s powerful, mid-range flash memory family of microcontrollers. 24.13 demonstration, development and evaluation boards a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart ? battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. check the microchip web page (www.microchip.com) and the latest ?product selector guide? (ds00148) for the complete list of demonstration, development and evaluation kits. ? 2007 microchip technology inc. preliminary ds39774c-page 339 pic18f85j11 family 25.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +100c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any digital only i/o pin or mclr with respect to v ss (except v dd ) ........................................... -0.3v to 6.0v voltage on any combined digital and analog pin with respect to v ss (except v dd and mclr )...... -0.3v to (v dd + 0.3v) voltage on v ddcore with respect to v ss ................................................................................................... -0.3v to 2.75v voltage on v dd with respect to v ss ........................................................................................................... -0.3v to 3.6v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma maximum output current sunk by porta<7:6> and any portb and portc i/o pins.........................................25 ma maximum output current sunk by any portd, porte and portj i/o pins ..........................................................8 ma maximum output current sunk by porta<5:0> and any portf, portg and porth i/o pins ............................2 ma maximum output current sourced by porta<7:6> and any portb and portc i/o pins ...................................25 ma maximum output current sourced by any portd, porte and portj i/o pins .....................................................8 ma maximum output current sourced by porta<5:0> and any portf, portg and porth i/o pins .......................2 ma maximum current sunk by all ports combined.......................................................................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } + (v ol x i ol ) ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. pic18f85j11 family ds39774c-page 340 preliminary ? 2007 microchip technology inc. figure 25-1: pic18f85j11 family voltage-frequency graph, regulator enabled (industrial) (1) figure 25-2: pic18f85j11 family voltage-frequency graph, regulator disabled (industrial) (1,2) frequency voltage (v dd ) 4.0v 2.0v 40 mhz 3.5v 3.0v 2.5v 3.6v pic18f6xj11/8xj11 2.35v 0 note 1: when the on-chip regulator is enabled, its bor circuit will automatically trigger a device reset before v dd reaches a level at which full-speed operation is not possible. 8 mhz frequency voltage (v ddcore ) 3.00v 2.00v 40 mhz 2.75v 2.50v 2.25v 2.7v 8 mhz 2.35v note 1: for frequencies between 4 mhz and 40 mhz, f max = (51.42 mhz/v) * (v ddcore ? 2v) + 4 mhz. 2: when the on-chip voltage regulator is disabled, v dd and v ddcore must be maintained so that v ddcore v dd 3.6v. pic18f6xj11/8xj11 ? 2007 microchip technology inc. preliminary ds39774c-page 341 pic18f85j11 family 25.1 dc characteristics: supply voltage pic18f85j11 family (industrial) pic18f85j11 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min typ max units conditions d001 v dd supply voltage v ddcore 2.0 ? ? 3.6 3.6 v v envreg tied to v ss envreg tied to v dd d001b v ddcore external supply for microcontroller core 2.0 ? 2.70 v envreg tied to v ss d001c av dd analog supply voltage v dd ? 0.3 ? v dd + 0.3 v d001d av ss analog ground potential v ss ? 0.3 ? v ss + 0.3 v d002 v dr ram data retention voltage (1) 1.5 ? ? v d003 v por v dd start voltage to ensure internal power-on reset signal ??0.7vsee section 4.3 ?power-on reset (por)? for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section 4.3 ?power-on reset (por)? for details d005 v bor brown-out reset voltage ?1.9?v note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. pic18f85j11 family ds39774c-page 342 preliminary ? 2007 microchip technology inc. 25.2 dc characteristics: power-down and supply current pic18f85j11 family (industrial) pic18f85j11 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions power-down current (i pd ) (1) all devices 0.2 0.9 a -40c v dd = 2.0v, v ddcore = 2.0v ( sleep mode) (4) 0.1 0.9 a +25c 2.4 5 a +85c all devices 0.5 0.9 a -40c v dd = 2.5v, v ddcore = 2.5v ( sleep mode) (4) 0.1 0.9 a +25c 2.7 5 a +85c all devices 2.7 6 a -40c v dd = 3.3v ( sleep mode) (5) 3.5 6 a +25c 6.7 12 a +85c legend: tbd = to be determined note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operatin g temperature range of -10c to +70c. extended tem- perature crystals are available at a much higher cost. 4: voltage regulator disabled (envreg tied to v ss ). 5: voltage regulator enabled (envreg tied to v dd ). ? 2007 microchip technology inc. preliminary ds39774c-page 343 pic18f85j11 family supply current (i dd ) (2) all devices 6.5 16 a -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 31 khz ( rc_run mode, internal oscillator source) 7 16 a +25c 9.5 20 a +85c all devices 10 18 a -40c v dd = 2.5v, v ddcore = 2.5v (4) 10.5 18 a +25c 12.5 24 a +85c all devices 41 100 a -40c v dd = 3.3v (5) 52 100 a +25c 71 110 a +85c all devices 359 750 a -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 1 mhz ( intosc_run mode, internal oscillator source) 387 750 a +25c 407 840 a +85c all devices 438 850 a -40c v dd = 2.5v, v ddcore = 2.5v (4) 470 850 a +25c 491 910 a +85c all devices 486 900 a -40c v dd = 3.3v (5) 526 900 a +25c 564 990 a +85c all devices 0.76 1.45 ma -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 4 mhz ( intosc_run mode, internal oscillator source) 0.84 1.45 ma +25c 0.9 1.6 ma +85c all devices 1.1 1.63 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) 1.18 1.63 ma +25c 1.24 1.75 ma +85c all devices 1.25 1.86 ma -40c v dd = 3.3v (5) 1.29 1.86 ma +25c 1.37 1.94 ma +85c 25.2 dc characteristics: power-down and supply current pic18f85j11 family (industrial) (continued) pic18f85j11 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: tbd = to be determined note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operatin g temperature range of -10c to +70c. extended tem- perature crystals are available at a much higher cost. 4: voltage regulator disabled (envreg tied to v ss ). 5: voltage regulator enabled (envreg tied to v dd ). pic18f85j11 family ds39774c-page 344 preliminary ? 2007 microchip technology inc. supply current (i dd ) (2) all devices 2.4 8 a -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 31 khz ( rc_idle mode, internal oscillator source) 2.5 8 a +25c 4.8 12 a +85c all devices 3.2 9 a -40c v dd = 2.5v, v ddcore = 2.5v (4) 3.2 9 a +25c 6 14 a +85c all devices 62 82 a -40c v dd = 3.3v (5) 42 82 a +25c 59 97 a +85c all devices 251 570 a -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 1 mhz ( intosc_idle mode, internal oscillator source) 264 570 a +25c 272 590 a +85c all devices 284 610 a -40c v dd = 2.5v, v ddcore = 2.5v (4) 284 610 a +25c 293 650 a +85c all devices 295 710 a -40c v dd = 3.3v (5) 323 710 a +25c 392 790 a +85c all devices 368 760 a -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 4 mhz ( intosc_idle mode, internal oscillator source) 362 760 a +25c 370 800 a +85c all devices 400 850 a -40c v dd = 2.5v, v ddcore = 2.5v (4) 410 850 a +25c 418 900 a +85c all devices 460 950 a -40c v dd = 3.3v (5) 462 950 a +25c 486 1,000 a +85c 25.2 dc characteristics: power-down and supply current pic18f85j11 family (industrial) (continued) pic18f85j11 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: tbd = to be determined note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operatin g temperature range of -10c to +70c. extended tem- perature crystals are available at a much higher cost. 4: voltage regulator disabled (envreg tied to v ss ). 5: voltage regulator enabled (envreg tied to v dd ). ? 2007 microchip technology inc. preliminary ds39774c-page 345 pic18f85j11 family supply current (i dd ) (2) all devices 165 490 a -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 1 mh z ( pri_run mode, ec oscillator) 180 490 a +25c 200 490 a +85c all devices 256 670 a -40c v dd = 2.5v, v ddcore = 2.5v (4) 260 670 a +25c 280 670 a +85c all devices 460 850 a -40c v dd = 3.3v (5) 456 850 a +25c 482 850 a +85c all devices 0.63 2.2 ma -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 4 mhz ( pri_run mode, ec oscillator) 0.68 2.2 ma +25c 0.74 2.2 ma +85c all devices 0.91 2.5 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) 1.04 2.5 ma +25c 1.04 2.5 ma +85c all devices 1.32 3.0 ma -40c v dd = 3.3v (5) 1.32 3.0 ma +25c 1.41 3.0 ma +85c all devices 7.47 14 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) f osc = 40 mh z ( pri_run mode, ec oscillator) 5.81 14 ma +25c 6.32 13 ma +85c all devices 8.84 18 ma -40c v dd = 3.3v (5) 8.66 18 ma +25c 7.97 16 ma +85c 25.2 dc characteristics: power-down and supply current pic18f85j11 family (industrial) (continued) pic18f85j11 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: tbd = to be determined note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operatin g temperature range of -10c to +70c. extended tem- perature crystals are available at a much higher cost. 4: voltage regulator disabled (envreg tied to v ss ). 5: voltage regulator enabled (envreg tied to v dd ). pic18f85j11 family ds39774c-page 346 preliminary ? 2007 microchip technology inc. supply current (i dd ) (2) all devices 2.8 3.8 ma -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 4 mh z , 16 mhz internal ( pri_run mode, hspll oscillator) 3.02 3.8 ma +25c 3.01 4.5 ma +85c all devices 4.5 5.4 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) f osc = 4 mh z , 16 mhz internal ( pri_run mode, hspll oscillator) 4.8 5.6 ma +25c 4.54 5.6 ma +85c all devices 5.72 6.7 ma -40c v dd = 3.3v (5) f osc = 4 mh z , 16 mhz internal ( pri_run mode, hspll oscillator) 5.55 6.5 ma +25c 5.3 6.5 ma +85c all devices 7.4 8.5 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) f osc = 10 mh z , 40 mhz internal ( pri_run mode, hspll oscillator) 7.23 8.5 ma +25c 6.55 7.5 ma +85c all devices 9.74 11.6 ma -40c v dd = 3.3v (5) f osc = 10 mh z , 40 mhz internal ( pri_run mode, hspll oscillator) 9.43 11.6 ma +25c 8.89 10.5 ma +85c 25.2 dc characteristics: power-down and supply current pic18f85j11 family (industrial) (continued) pic18f85j11 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: tbd = to be determined note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operatin g temperature range of -10c to +70c. extended tem- perature crystals are available at a much higher cost. 4: voltage regulator disabled (envreg tied to v ss ). 5: voltage regulator enabled (envreg tied to v dd ). ? 2007 microchip technology inc. preliminary ds39774c-page 347 pic18f85j11 family supply current (i dd ) (2) all devices 50 120 a -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 1 mhz ( pri_idle mode, ec oscillator) 51 120 a +25c 54 130 a +85c all devices 223 480 a -40c v dd = 2.5v, v ddcore = 2.5v (4) 134 300 a +25c 110 270 a +85c all devices 307 550 a -40c v dd = 3.3v (5) 254 500 a +25c 194 460 a +85c all devices 307 850 a -40c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 4 mhz ( pri_idle mode, ec oscillator) 200 850 a +25c 202 800 a +85c all devices 483 950 a -40c v dd = 2.5v, v ddcore = 2.5v (4) 318 950 a +25c 343 900 a +85c all devices 0.52 1.3 ma -40c v dd = 3.3v (5) 0.47 1.2 ma +25c 0.47 1.2 ma +85c all devices 2.38 8 ma -40c v dd = 2.5v, v ddcore = 2.5v (4) f osc = 40 mhz ( pri_idle mode, ec oscillator) 2.04 8 ma +25c 2.52 9 ma +85c all devices 3.02 10 ma -40c v dd = 3.3v (5) 2.99 10 ma +25c 4.23 11 ma +85c 25.2 dc characteristics: power-down and supply current pic18f85j11 family (industrial) (continued) pic18f85j11 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: tbd = to be determined note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operatin g temperature range of -10c to +70c. extended tem- perature crystals are available at a much higher cost. 4: voltage regulator disabled (envreg tied to v ss ). 5: voltage regulator enabled (envreg tied to v dd ). pic18f85j11 family ds39774c-page 348 preliminary ? 2007 microchip technology inc. supply current (i dd ) (2) all devices 10.5 22 a -10c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 32 khz (3) ( sec_run mode, timer1 as clock) 13.4 28 a +25c 17.6 40 a +70c all devices 13.2 30 a -10c v dd = 2.5v, v ddcore = 2.5v (4) 16.2 35 a +25c 20.7 50 a +70c all devices 39 120 a -10c v dd = 3.3v (5) 58 150 a +25c 75 190 a +70c all devices 5.7 15 a -10c v dd = 2.0v, v ddcore = 2.0v (4) f osc = 32 khz (3) ( sec_idle mode, timer1 as clock) 8.9 20 a +25c 12.8 26 a +70c all devices 6.6 17 a -10c v dd = 2.5v, v ddcore = 2.5v (4) 9.7 24 a +25c 13.7 30 a +70c all devices 39 115 a -10c v dd = 3.3v (5) 52.8 145 a +25c 72.7 185 a +70c 25.2 dc characteristics: power-down and supply current pic18f85j11 family (industrial) (continued) pic18f85j11 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: tbd = to be determined note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operatin g temperature range of -10c to +70c. extended tem- perature crystals are available at a much higher cost. 4: voltage regulator disabled (envreg tied to v ss ). 5: voltage regulator enabled (envreg tied to v dd ). ? 2007 microchip technology inc. preliminary ds39774c-page 349 pic18f85j11 family d022 ( i wdt ) module differential currents ( i wdt , i oscb , i ad ) watchdog timer 1.6 4 a -40c v dd = 2.0v, v ddcore = 2.0v (4) 1.7 4 a +25c 1.6 4 a +85c 2.5 5 a -40c v dd = 2.5v, v ddcore = 2.5v (4) 2.5 5 a +25c 2.3 5 a +85c 3.8 6 a -40c v dd = 3.3v (5) 2.6 6 a +25c 2.4 6 a +85c d025 ( i oscb ) timer1 oscillator 6.6 12.5 a -40c v dd = 2.0v, v ddcore = 2.0v (4) 32 khz on timer1 (3) 7.9 12.5 a +25c 11.5 18 a +85c 7.2 12.5 a -40c v dd = 2.5v, v ddcore = 2.5v (4) 32 khz on timer1 (3) 8.1 12.5 a +25c 11.9 18.5 a +85c 7 12.5 a -40c v dd = 3.3v (5) 32 khz on timer1 (3) 9 12.5 a +25c 11 18.5 a +85c d026 ( i ad ) a/d converter 1 1.5 a -40c to +85c v dd = 2.0v, v ddcore = 2.0v (4) a/d on, not converting 1 1.5 a -40c to +85c v dd = 2.5v, v ddcore = 2.5v (4) 1 1.5 a -40c to v dd = 3.3v (5) 25.2 dc characteristics: power-down and supply current pic18f85j11 family (industrial) (continued) pic18f85j11 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: tbd = to be determined note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operatin g temperature range of -10c to +70c. extended tem- perature crystals are available at a much higher cost. 4: voltage regulator disabled (envreg tied to v ss ). 5: voltage regulator enabled (envreg tied to v dd ). pic18f85j11 family ds39774c-page 350 preliminary ? 2007 microchip technology inc. 25.3 dc characteristics: pic18f85j11 family (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min max units conditions v il input low voltage all i/o ports: d030 with ttl buffer v ss 0.15 v dd v d031 with schmitt trigger buffer v ss 0.2 v dd v d032 mclr v ss 0.2 v dd v d033 osc1 v ss 0.3 v dd v hs, hspll modes d033a d034 osc1 t13cki v ss v ss 0.2 v dd 0.3 v v ec, ecpll modes (1) v ih input high voltage i/o ports with analog functions: d040 with ttl buffer 0.25 v dd + 0.8v v dd vv dd < 3.3v d041 with schmitt trigger buffer 0.8 v dd v dd v digital only i/o ports: dxxx with ttl buffer 0.25 v dd + 0.8v 5.5 v v dd < 3.3v dxxxa 2.0 5.5 v 3.3v v dd 3.6v dxxx with schmitt trigger buffer 0.8 v dd 5.5 v d042 mclr 0.8 v dd v dd v d043 osc1 0.7 v dd v dd v hs, hspll modes d043a d044 osc1 t13cki 0.8 v dd 1.6 v dd v dd v v ec, ecpll modes i il input leakage current (1) d060 i/o ports ? 1av ss v pin v dd , pin at high-impedance d061 mclr ? 1avss v pin v dd d063 osc1 ? 1avss v pin v dd i pu weak pull-up current d070 i purb portb weak pull-up current 30 240 a v dd = 3.3v, v pin = v ss note 1: negative current is defined as current sourced by the pin. ? 2007 microchip technology inc. preliminary ds39774c-page 351 pic18f85j11 family v ol output low voltage d080 i/o ports: porta, portf, portg, porth ?0.4vi ol = 2 ma, v dd = 3.3v, -40 c to +85 c portd, porte, portj ? 0.4 v i ol = 3.4 ma, v dd = 3.3v, -40 c to +85 c portb, portc ? 0.4 v i ol = 3.4 ma, v dd = 3.3v, -40 c to +85 c d083 osc2/clko (ec, ecpll modes) ?0.4vi ol = 1.6 ma, v dd = 3.3v, -40 c to +85 c v oh output high voltage (1) d090 i/o ports: v porta, portf, portg, porth 2.4 ? v i oh = -2 ma, v dd = 3.3v, -40 c to +85 c portd, porte, portj 2.4 ? v i oh = -2 ma, v dd = 3.3v, -40 c to +85 c portb, portc 2.4 ? v i oh = -2 ma, v dd = 3.3v, -40 c to +85 c d092 osc2/clko (intosc, ec, ecpll modes) 2.4 ? v i oh = -1 ma, v dd = 3.3v, -40 c to +85 c capacitive loading specs on output pins d100 cosc2 osc2 pin ? 15 pf in hs mode when external clock is used to drive osc1 d101 c io all i/o pins and osc2 ? 50 pf to meet the ac timing specifications d102 c b sclx, sdax ? 400 pf i 2 c? specification 25.3 dc characteristics: pic18f85j11 family (industrial) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min max units conditions note 1: negative current is defined as current sourced by the pin. pic18f85j11 family ds39774c-page 352 preliminary ? 2007 microchip technology inc. table 25-1: memory programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. sym characteristic min typ? max units conditions program flash memory d130 e p cell endurance 100 1k ? e/w -40 c to +85 c d131 v pr v dd for read v min ?3.6vv min = minimum operating voltage d132b v pew v dd for self-timed write v min ?3.6vv min = minimum operating voltage d133a t iw self-timed write cycle time ? 2.8 ? ms d134 t retd characteristic retention 20 ? ? year provided no other specifications are violated d135 i ddp supply current during programming ?3 7ma d1xxx t we writes per erase cycle ? ? 1 per one physical word address ? data in ?typ? column is at 3.3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ? 2007 microchip technology inc. preliminary ds39774c-page 353 pic18f85j11 family table 25-2: comparator specifications table 25-3: voltage reference specifications table 25-4: internal voltage regulator specifications operating conditions: 3.0v v dd 3.6v, -40c t a +85c (unless otherwise stated) param no. sym characteristics min typ max units comments d300 v ioff input offset voltage ? 5.0 10 mv d301 v icm input common mode voltage* 0 ? av dd ? 1.5 v d302 cmrr common mode rejection ratio* 55 ? ? db 300 t resp response time* (1) ?150400 ns 301 t mc 2 ov comparator mode change to output valid* ?? 10s * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (av dd ? 1.5)/2, while the other input transitions from v ss to v dd . operating conditions: 3.0v v dd 3.6v, -40c t a +85c (unless otherwise stated) param no. sym characteristics min typ max units comments d310 v res resolution v dd /24 ? v dd /32 lsb d311 vr aa absolute accuracy ? ? 1/2 lsb d312 vr ur unit resistor value (r) ? 2k ? 310 t set settling time (1) ? ? 10 s note 1: settling time measured while cvrr = 1 and cvr3:cvr0 bits transition from ? 0000 ? to ? 1111 ?. operating conditions: -40c t a +85c (unless otherwise stated) param no. sym characteristics min typ max units comments v rgout regulator output voltage* ? 2.5 ? v c efc external filter capacitor value* 4.7 10 ? f capacitor must be low-esr * these parameters are characterized but not tested. parameter numbers not yet assigned for these specifications. pic18f85j11 family ds39774c-page 354 preliminary ? 2007 microchip technology inc. 25.4 ac (timing) characteristics 25.4.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clko rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t13cki mc mclr wr wr uppercase letters and their meanings: s f fall p period hhigh rrise i invalid (high-impedance) v valid l low z high-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition ? 2007 microchip technology inc. preliminary ds39774c-page 355 pic18f85j11 family 25.4.2 timing conditions the temperature and voltages specified in table 25-5 apply to all timing specifications unless otherwise noted. figure 25-3 specifies the load conditions for the timing specifications. table 25-5: temperature and voltage specifications ? ac figure 25-3: load conditions for devi ce timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial operating voltage v dd range as described in section 25.1 and section 25.3 . v dd /2 c l r l pin pin v ss v ss c l r l =464 c l = 50 pf for all pins except ra6/osc2/clko and including d and e outputs as ports c l = 15 pf for ra6/osc2/clko load condition 1 load condition 2 pic18f85j11 family ds39774c-page 356 preliminary ? 2007 microchip technology inc. 25.4.3 timing diagrams and specifications figure 25-4: external clock timing (all modes except pll) table 25-6: external clock timing requirements osc1 clko q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 param. no. symbol characteristic min max units conditions 1a f osc external clki frequency (1) dc 40 mhz ecpll oscillator mode oscillator frequency (1) dc 40 mhz hspll oscillator mode 1t osc external clki period (1) 25 ? ns ec oscillator mode oscillator period (1) 25 250 ns hs oscillator mode 2t cy instruction cycle time (1) 100 ? ns t cy = 4/f osc , industrial 3t os l, t os h external clock in (osc1) high or low time 10 ? ns ec oscillator mode 4t os r, t os f external clock in (osc1) rise or fall time ? 7.5 ns ec oscillator mode note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period for all configurations except pll. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices. ? 2007 microchip technology inc. preliminary ds39774c-page 357 pic18f85j11 family table 25-7: pll clock timing specifications (v dd = 2.15v to 3.6v) table 25-8: internal rc accuracy (intosc and intrc sources) param no. sym characteristic min typ? max units conditions f10 f osc oscillator frequency range 4 ? 10 mhz hs mode only f11 f sys on-chip vco system frequency 16 ? 40 mhz hs mode only f12 t rc pll start-up time (lock time) ? ? 2 ms f13 clk clko stability (jitter) -2 ? +2 % ? data in ?typ? column is at 3.3v, 25 c, unless otherwise stated. these parameters are for design guidance only and are not tested. pic18f85j11 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device min typ max units conditions intosc accuracy @ freq = 8 mhz, 4 mhz, 2 mhz, 1 mhz, 500 khz, 250 khz, 125 khz, 31 khz (1) all devices -2 +/-1 2 % +25c v dd = 2.7-3.3v -5 ? 5 % -10c to +85c v dd = 2.0-3.3v -10 +/-1 10 % -40c to +85c v dd = 2.0-3.3v intrc accuracy @ freq = 31 khz (1) all devices 26.562 ? 35.938 khz -40c to +85c v dd = 2.0-3.3v legend: tbd = to be determined note 1: the accuracy specification of the 31 khz clock is determined by which source is providing it at a given time. when intsrc (osctune<7>) is ? 1 ?, use the intosc accuracy specification. when intsrc is ? 0 ?, use the intrc accuracy specification. pic18f85j11 family ds39774c-page 358 preliminary ? 2007 microchip technology inc. figure 25-5: clko and i/o timing table 25-9: clko and i/o timing requirements note: refer to figure 25-3 for load conditions. osc1 clko i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value param no. symbol characteristic min typ max units conditions 10 t os h2 ck losc1 to clko ?75200ns (note 1) 11 t os h2 ck hosc1 to clko ?75200ns (note 1) 12 t ck rclko rise time ? 15 30 ns (note 1) 13 t ck f clko fall time ? 15 30 ns (note 1) 14 t ck l2 io vclko to port out valid ? ? 0.5 t cy + 20 ns 15 t io v2 ck h port in valid before clko 0.25 t cy + 25 ? ? ns 16 t ck h2 io i port in hold after clko 0??ns 17 t os h2 io vosc1 (q1 cycle) to port out valid ? 50 150 ns 18 t os h2 io iosc1 (q2 cycle) to port input invalid (i/o in hold time) 100 ? ? ns 19 t io v2 os h port input valid to osc1 (i/o in setup time) 0??ns 20 t io r port output rise time ? ? 6 ns 21 t io f port output fall time ? ? 5 ns 22? t inp intx pin high or low time t cy ??ns 23? t rbp rb7:rb4 change intx high or low time t cy ??ns ? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in ec mode, where clko output is 4 x t osc . ? 2007 microchip technology inc. preliminary ds39774c-page 359 pic18f85j11 family figure 25-6: reset, watchdog timer, oscillator start-up timer and power-up timer timing table 25-10: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements param no. symbol characteristic min typ max units conditions 30 t mc lmclr pulse width (low) 2 t cy 10 t cy ? (note 1) 31 t wdt watchdog timer time-out period (no postscaler) 3.4 4.0 4.6 ms 32 t ost oscillator start-up timer period 1024 t osc ? 1024 t osc t osc = osc1 period 33 t pwrt power-up timer period 45.8 65.5 85.2 ms 34 t ioz i/o high-impedance from mclr low or watchdog timer reset ?2? s 38 t csd cpu start-up time ? 10 ? s ? 200 ? s voltage regulator enabled and put to sleep 39 t iobst time for intosc to stabilize ? 1 ? s note 1: to ensure device reset, mclr must be low for at least 2 t cy or 400 s, which ever is lower. v dd mclr internal por pwrt time-out oscillator time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 25-3 for load conditions. pic18f85j11 family ds39774c-page 360 preliminary ? 2007 microchip technology inc. figure 25-7: timer0 and timer1 external clock timings table 25-11: timer0 and timer1 external clock requirements note: refer to figure 25-3 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t13cki tmr0 or tmr1 param no. symbol characteristic min max units conditions 40 t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 41 t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 42 t t 0p t0cki period no prescaler t cy + 10 ? ns with prescaler greater of: 20 ns or (t cy + 40)/n ?nsn = prescale value (1, 2, 4,..., 256) 45 t t 1h t13cki high time synchronous, no prescaler 0.5 t cy + 20 ? ns synchronous, with prescaler 10 ? ns asynchronous 30 ? ns 46 t t 1l t13cki low time synchronous, no prescaler 0.5 t cy + 5 ? ns synchronous, with prescaler 10 ? ns asynchronous 30 ? ns 47 t t 1p t13cki input period synchronous greater of: 20 ns or (t cy + 40)/n ?nsn = prescale value (1, 2, 4, 8) asynchronous 60 ? ns f t 1 t13cki oscillator input frequency range dc 50 khz 48 t cke 2 tmr i delay from external t13cki clock edge to timer increment 2 t osc 7 t osc ? ? 2007 microchip technology inc. preliminary ds39774c-page 361 pic18f85j11 family figure 25-8: capture/compare/pwm timi ngs (ccp1, ccp2 modules) table 25-12: capture/compare/pwm requirements (ccp1, ccp2 modules) note: refer to figure 25-3 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode) param no. symbol characteristic min max units conditions 50 t cc l ccpx input low time no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 51 t cc h ccpx input high time no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 52 t cc p ccpx input period 3 t cy + 40 n ? ns n = prescale value (1, 4 or 16) 53 t cc r ccpx output fall time ? 25 ns 54 t cc f ccpx output fall time ? 25 ns pic18f85j11 family ds39774c-page 362 preliminary ? 2007 microchip technology inc. figure 25-9: example spi ma ster mode timing (cke = 0 ) table 25-13: example spi mode requirements (master mode, cke = 0 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit 6 - - - - - - 1 lsb in bit 6 - - - - 1 note: refer to figure 25-3 for load conditions. msb in param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ss to sck or sck input t cy ?ns 71 t sc h sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ns 75 t do r sdo data output rise time ? 25 ns 76 t do f sdo data output fall time ? 25 ns 78 t sc r sck output rise time (master mode) ? 25 ns 79 t sc f sck output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge ? 50 ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ? 2007 microchip technology inc. preliminary ds39774c-page 363 pic18f85j11 family figure 25-10: example spi master mode timing (cke = 1 ) table 25-14: example spi mode requirements (master mode, cke = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 bit 6 - - - - - - 1 lsb in bit 6 - - - - 1 lsb note: refer to figure 25-3 for load conditions. msb in param. no. symbol characteristic min max units conditions 71 t sc h sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ns 75 t do r sdo data output rise time ? 25 ns 76 t do f sdo data output fall time ? 25 ns 78 t sc r sck output rise time (master mode) ? 25 ns 79 t sc f sck output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge ? 50 ns 81 t do v2 sc h, t do v2 sc l sdo data output setup to sck edge t cy ?ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. pic18f85j11 family ds39774c-page 364 preliminary ? 2007 microchip technology inc. figure 25-11: example spi slave mode timing (cke = 0 ) table 25-15: example spi mode requirements (slave mode timing, cke = 0 ) param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ss to sck or sck input 3 t cy ?ns 70a t ss l2wb ss to write to sspbuf 3 t cy ?ns 71 t sc h sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the first clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ns 75 t do r sdo data output rise time ? 25 ns 76 t do f sdo data output fall time ? 25 ns 77 t ss h2 do zss to sdo output high-impedance 10 50 ns 78 t sc r sck output rise time (master mode) ? 25 ns 79 t sc f sck output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge ? 50 ns 83 t sc h2 ss h, t sc l2 ss h ss after sck edge 1.5 t cy + 40 ? ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 msb lsb bit 6 - - - - - - 1 bit 6 - - - - 1 lsb in 83 note: refer to figure 25-3 for load conditions. msb in ? 2007 microchip technology inc. preliminary ds39774c-page 365 pic18f85j11 family figure 25-12: example spi slave mode timing (cke = 1 ) table 25-16: example spi slave mode requirements (cke = 1 ) param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ss to sck or sck input 3 t cy ?ns 70a t ss l2wb ss to write to sspbuf 3 t cy ?ns 71 t sc h sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73a t b 2 b last clock edge of byte 1 to the first clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ns 75 t do r sdo data output rise time ? 25 ns 76 t do f sdo data output fall time ? 25 ns 77 t ss h2 do zss to sdo output high-impedance 10 50 ns 78 t sc r sck output rise time (master mode) ? 25 ns 79 t sc f sck output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge ? 50 ns 82 t ss l2 do v sdo data output valid after ss edge ? 50 ns 83 t sc h2 ss h, t sc l2 ss h ss after sck edge 1.5 t cy + 40 ? ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 71 72 82 74 75, 76 msb bit 6 - - - - - - 1 lsb 77 bit 6 - - - - 1 lsb in 80 83 note: refer to figure 25-3 for load conditions. msb in 70 pic18f85j11 family ds39774c-page 366 preliminary ? 2007 microchip technology inc. figure 25-13: i 2 c? bus start/stop bits timing table 25-17: i 2 c? bus start/stop bits requirements (slave mode) note: refer to figure 25-3 for load conditions. 91 92 93 scl sda start condition stop condition 90 param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? 91 t hd : sta start condition 100 khz mode 4000 ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? 92 t su : sto stop condition 100 khz mode 4700 ? ns setup time 400 khz mode 600 ? 93 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? ? 2007 microchip technology inc. preliminary ds39774c-page 367 pic18f85j11 family figure 25-14: i 2 c? bus data timing table 25-18: i 2 c? bus data requirements (slave mode) param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 ? s 400 khz mode 0.6 ? s mssp module 1.5 t cy ? 101 t low clock low time 100 khz mode 4.7 ? s 400 khz mode 1.3 ? s mssp module 1.5 t cy ? 102 t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 91 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? s 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 109 t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns 110 t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s d102 c b bus capacitive loading ? 400 pf note 1: as a transmitter, the device must provide this internal mi nimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode i 2 c? bus device can be used in a standard mode i 2 c bus system, but the requirement, t su : dat 250 ns, must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line, t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) , before the scl line is released. note: refer to figure 25-3 for load conditions. 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out 90 pic18f85j11 family ds39774c-page 368 preliminary ? 2007 microchip technology inc. figure 25-15: mssp i 2 c? bus start/stop bits timing waveforms table 25-19: mssp i 2 c? bus start/stop bits requirements figure 25-16: mssp i 2 c? bus data timing param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns only relevant for repeated start condition setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 91 t hd : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns after this period, the first clock pulse is generated hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 92 t su : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 93 t hd : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? note 1: maximum pin capacitance = 10 pf for all i 2 c? pins. note: refer to figure 25-3 for load conditions. 91 93 scl sda start condition stop condition 90 92 note: refer to figure 25-3 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out ? 2007 microchip technology inc. preliminary ds39774c-page 369 pic18f85j11 family table 25-20: mssp i 2 c? bus data requirements param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 101 t low clock low time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 102 t r sda and scl rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 300 ns 103 t f sda and scl fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 100 ns 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) ? ms after this period, the first clock pulse is generated 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ms 1 mhz mode (1) tbd ? ns 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 1 mhz mode (1) tbd ? ns 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 109 t aa output valid from clock 100 khz mode ? 3500 ns 400 khz mode ? 1000 ns 1 mhz mode (1) ??ns 110 t buf bus free time 100 khz mode 4.7 ? ms time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ms 1 mhz mode (1) tbd ? ms d102 c b bus capacitive loading ? 400 pf legend: tbd = to be determined note 1: maximum pin capacitance = 10 pf for all i 2 c? pins. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but parameter #107 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 khz mode), before the scl line is released. pic18f85j11 family ds39774c-page 370 preliminary ? 2007 microchip technology inc. figure 25-17: eusart/ausart synchronous transmission (master/slave) timing table 25-21: eusart/ausart synchronous transmission requirements figure 25-18: eusart/ausart synchronous receiv e (master/slave) timing table 25-22: eusart/ausart synchronous receive requirements 121 121 120 122 txx/ckx rxx/dtx pin pin note: refer to figure 25-3 for load conditions. param no. symbol characteristic min max units conditions 120 t ck h2 dt v sync xmit (master and slave) clock high to data out valid ? 40 ns 121 t ckrf clock out rise time and fall time (master mode) ? 20 ns 122 t dtrf data out rise time and fall time ? 20 ns 125 126 txx/ckx rxx/dtx pin pin note: refer to figure 25-3 for load conditions. param. no. symbol characteristic min max units conditions 125 t dt v2 ckl sync rcv (master and slave) data hold before ckx (dtx hold time) 10 ? ns 126 t ck l2 dtl data hold after ckx (dtx hold time) 15 ? ns ? 2007 microchip technology inc. preliminary ds39774c-page 371 pic18f85j11 family table 25-23: a/d converter characteristics: pic18f85j11 family (industrial) param no. symbol characteristic min typ max units conditions a01 n r resolution ? ? 10 bits a03 e il integral linearity error ? ? <1 lsb v ref 3.0v a04 e dl differential linearity error ? ? <1 lsb v ref 3.0v a06 e off offset error ? ? <3 lsb v ref 3.0v a07 e gn gain error ? ? <3 lsb v ref 3.0v a10 ? monotonicity guaranteed (1) ?v ss v ain v ref a20 v ref reference voltage range (v refh ? v refl ) 2.0 3 ? ? ? ? v v v dd < 3.0v v dd 3.0v a21 v refh reference voltage high v ss ?v refh v a22 v refl reference voltage low v ss ? 0.3v ? v dd ? 3.0v v a25 v ain analog input voltage v refl ?v refh v a30 z ain recommended impedance of analog voltage source ??2.5k a50 i ref v ref input current (2) ? ? ? ? 5 150 a a during v ain acquisition during a/d conversion cycle note 1: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 2: v refh current is from ra3/an3/v ref + pin or v dd , whichever is selected as the v refh source. v refl current is from ra2/an2/v ref - pin or v ss , whichever is selected as the v refl source. pic18f85j11 family ds39774c-page 372 preliminary ? 2007 microchip technology inc. figure 25-19: a/d conversion timing table 25-24: a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (note 2) 987 21 0 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . t cy (note 1) param no. symbol characteristic min max units conditions 130 t ad a/d clock period 0.7 25.0 (1) s t osc based, v ref 3.0v tbd 1 s a/d rc mode 131 t cnv conversion time (not including acquisition time) (2) 11 12 t ad 132 t acq acquisition time (3) 1.4 ? ? s -40 c to +85 c 135 t swc switching time from convert sample ? (note 4) tbd t dis discharge time 0.2 ? s legend: tbd = to be determined note 1: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider. 2: adres registers may be read on the following t cy cycle. 3: the time for the holding capacitor to acquire the ?new? input voltage when the voltage changes full scale after the conversion (v dd to v ss or v ss to v dd ). the source impedance (r s ) on the input channels is 50 . 4: on the following cycle of the device clock. ? 2007 microchip technology inc. preliminary ds39774c-page 373 pic18f85j11 family 26.0 dc and ac characteristics graphs and tables graphs and tables are not available at this time. pic18f85j11 family ds39774c-page 374 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. preliminary ds39774c-page 375 pic18f85j11 family 27.0 packaging information 27.1 package marking information 3 e 3 e 64-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example 18f65j11 -i/pt 0710017 80-lead tqfp xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic18f85j11 -i/pt 0710017 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e pic18f85j11 family ds39774c-page 376 preliminary ? 2007 microchip technology inc. 27.2 package details the following sections give the technical details of the packages. 64-lead plastic thin quad flatpack (pt) C 10x10x1 mm body, 2.00 mm footprint [tqfp] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. chamfers at corners are optional; size may vary. 3. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.25 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of leads n 64 lead pitch e 0.50 bsc overall height a ? ? 1.20 molded package thickness a2 0.95 1.00 1.05 standoff a1 0.05 ? 0.15 foot length l 0.45 0.60 0.75 footprint l1 1.00 ref foot angle 0 3.5 7 overall width e 12.00 bsc overall length d 12.00 bsc molded package width e1 10.00 bsc molded package length d1 10.00 bsc lead thickness c 0.09 ? 0.20 lead width b 0.17 0.22 0.27 mold draft angle top 11 12 13 mold draft angle bottom 11 12 13 d d1 e e1 e b n note 1 12 3 note 2 c l a1 l1 a2 a microchip technology drawing c04-085b ? 2007 microchip technology inc. preliminary ds39774c-page 377 pic18f85j11 family 80-lead plastic thin quad flatpack (pt) C 12x12x1 mm body, 2.00 mm footprint [tqfp] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. chamfers at corners are optional; size may vary. 3. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.25 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of leads n 80 lead pitch e 0.50 bsc overall height a ? ? 1.20 molded package thickness a2 0.95 1.00 1.05 standoff a1 0.05 ? 0.15 foot length l 0.45 0.60 0.75 footprint l1 1.00 ref foot angle 0 3.5 7 overall width e 14.00 bsc overall length d 14.00 bsc molded package width e1 12.00 bsc molded package length d1 12.00 bsc lead thickness c 0.09 ? 0.20 lead width b 0.17 0.22 0.27 mold draft angle top 11 12 13 mold draft angle bottom 11 12 13 d d1 e e1 e b n note 1 12 3 note 2 a a2 l1 a1 l c microchip technology drawing c04-092b pic18f85j11 family ds39774c-page 378 preliminary ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. ds39774c-page 379 pic18f85j11 family appendix a: revision history revision a (october 2006) original data sheet for pic18f85j11 family devices. revision b (march 2007) updated power-down and supply current electrical characteristics and package detail drawings. revision c (april 2007) updated electrical characteristics. appendix b: migration between high-end device families devices in the pic18f85j11 and pic18f8722 families are very similar in their functions and feature sets. how- ever, there are some potentially important differences which should be considered when migrating an applica- tion across device families to achieve a new design goal. these are summarized in table b-1. the areas of difference which could have a major impact on migration are discussed in greater detail later in this section. table b-1: notable differences between pic18f85j11 and pic18f8722 families characteristic pic18f85j11 family pic18f8722 family operating frequency 40 mhz @ 2.15v 40 mhz @ 4.2v supply voltage 2.0v-3.6v, dual voltage requirement 2.0v-5.5v operating current low lower program memory endurance 1,000 write/erase cycles (typical) 100,000 write/erase cycles (typical) i/o sink/source at 25 ma portb and portc only all ports input voltage tolerance on i/o pins 5.5v on digital only pins v dd on all i/o pins i/o 68 (rf0 is not available) 70 pull-ups portb, portd, porte and portj portb oscillator options limited options (ec, hs, pll, flexible intrc) more options (ec, hs, xt, lp, rc, pll, flexible intrc) program memory retention 20 years (minimum) 40 years (minimum) self-writes to program memory available available programming time (normalized) 156 s/byte (10 ms/64-byte block) 15.6 s/byte (1 ms/64) programming entry low voltage, key sequence v pp and lvp code protection single block, all or nothing multiple code protection blocks configuration words stored in last 4 words of program memory space stored in configuration space, starting at 300000h power-up timer always on configurable data eeprom use self-programming available bor simple bor with voltage regulator programmable bor lvd simple lvd with voltage regulator available a/d channels 12 16 a/d calibration required not required microprocessor mode (emb) self-calibration feature available external memory addressing address shifting available address shifting not available in-circuit emulation not available available pic18f85j11 family ds39774c-page 380 ? 2007 microchip technology inc. b.1 power requirement differences the most significant difference between the pic18f85j11 and pic18f8722 device families is the power requirements. pic18f85j11 devices are designed on a smaller process; this results in lower maximum voltage and higher leakage current. the operating voltage range for pic18f85j11 devices is 2.0v to 3.6v. in addition, these devices have split power requirements: one for the core logic and one for the i/o. one of the v dd pins is separated for the core logic supply, v ddcore . this pin has specific voltage and capacitor requirements as described in section 25.0 ?electrical characteristics? . the current specifications for pic18f85j11 devices are yet to be determined. b.2 pin differences there are several differences in the pinout between the pic18f85j11 and the pic18f8722 families: ? input voltage tolerance ? output current capabilities ? available i/o pins on the pic18f85j11 that have digital only input capability will tolerate voltages up to 5.5v and are thus tolerant to voltages above v dd . table 10-1 in section 10.1 ?i/o port pin capabilities? contains the complete list. in addition to input differences, there are output differ- ences as well. pic18f85j11 devices have three classes of pin output current capability: high, medium and low. not all i/o pins can source or sink equal levels of current. only portb and portc support the 25 ma source/sink capability that is supported by all output pins on the pic18f8722. table 10-2 in section 10.1 ?i/o port pin capabilities? contains the complete list of output capabilities. there are additional differences in how some pin func- tions are implemented on pic18f85j11 devices. first, the mclr pin is dedicated only to mclr and cannot be configured as an input (rg5). finally, rf0 does not exist on pic18f85j11 devices. all of these pin differences (including power pin differences) should be accounted for when making a conversion between pic18f8722 and pic18f85j11 devices. b.3 oscillator differences pic18f8722 and pic18f85j11 family devices share a similar range of oscillator options. the major difference is that pic18f85j11 family devices support a smaller number of primary (external) oscillator options, namely hs and ec oscillator modes. while both device families have an internal pll that can be used with the primary oscillators, the pll for the pic18f85j11 family is not enabled as a device configuration option. instead, it must be enabled in software. the clocking differences should be considered when making a conversion between the pic18f8722 and pic18f85j11 device families. b.4 peripherals peripherals must also be considered when making a conversion between the pic18f85j11 and the pic18f8722: ? external memory bus: the external memory bus (emb) on the pic18f85j11 does not support microcontroller mode; however, it does support external address offset. ? a/d converter: there are only 12 channels on pic18f85j11 devices. the converters for these devices also require a calibration step prior to normal operation. ? data eeprom: pic18f85j11 devices do not have this module. ? bor: pic18f85j11 devices do not have a programmable bor. simple brown-out reset capability is provided through the use of the internal voltage regulator. ? lvd: pic18f85j11 devices do not have a separate programmable lvd module. simple, low-voltage detection capability with a config- urable interrupt is provided through the use of the internal voltage regulator. ? 2007 microchip technology inc. preliminary ds39774c-page 381 pic18f85j11 family index a a/d ................................................................................... 251 a/d converter interrupt, configuring ....................... 255 acquisition requirements ........................................ 256 adcal bit ................................................................ 259 adcon0 register .................................................... 251 adcon1 register .................................................... 251 adcon2 register .................................................... 251 adresh register ............................................ 251, 254 adresl register .................................................... 251 analog port pins, configuring .................................. 257 associated registers ............................................... 259 automatic acquisition time ...................................... 257 configuring the module ............................................ 255 conversion clock (t ad ) ........................................... 257 conversion requirements ....................................... 372 conversion status (go/done bit) .......................... 254 conversions ............................................................. 258 converter calibration ............................................... 259 converter characteristics ........................................ 371 operation in power-managed modes ...................... 259 special event trigger (ccp2) .................................. 258 use of the ccp2 trigger .......................................... 258 absolute maximum ratings ............................................. 339 ac (timing) characteristics ............................................. 354 load conditions for device timing specifications ................................................... 355 parameter symbology ............................................. 354 temperature and voltage specifications ................................................... 355 timing conditions .................................................... 355 ackstat ........................................................................ 207 ackstat status flag ..................................................... 207 adcal bit ........................................................................ 259 adcon0 register ............................................................ 251 go/done bit ........................................................... 254 adcon1 register ............................................................ 251 adcon2 register ............................................................ 251 addfsr .......................................................................... 328 addlw ............................................................................ 291 addressable universal synchronous asynchronous receiver transmitter (ausart). see ausart. addulnk ........................................................................ 328 addwf ............................................................................ 291 addwfc ......................................................................... 292 adresh register ............................................................ 251 adresl register .................................................... 251, 254 analog-to-digital converter. see a/d. andlw ............................................................................ 292 andwf ............................................................................ 293 assembler mpasm assembler .................................................. 336 ausart asynchronous mode ................................................ 242 associated registers, receive ........................ 245 associated registers, transmit ....................... 243 receiver ........................................................... 244 setting up 9-bit mode with address detect ........................................ 244 transmitter ....................................................... 242 baud rate generator (brg) ................................... 240 associated registers ....................................... 240 baud rate error, calculating ........................... 240 baud rates, asynchronous modes ................. 241 high baud rate select (brgh bit) ................. 240 operation in power-managed modes .............. 240 sampling ......................................................... 240 control registers ..................................................... 237 synchronous master mode ...................................... 246 associated registers, receive ........................ 248 associated registers, transmit ....................... 247 reception ........................................................ 248 transmission ................................................... 246 synchronous slave mode ........................................ 249 associated registers, receive ........................ 250 associated registers, transmit ....................... 249 reception ........................................................ 250 transmission ................................................... 249 auto-wake-up on sync break character ......................... 230 b baud rate generator ...................................................... 203 bc .................................................................................... 293 bcf ................................................................................. 294 bf .................................................................................... 207 bf status flag ................................................................. 207 block diagrams 16-bit byte select mode ............................................ 99 16-bit byte write mode .............................................. 97 16-bit word write mode ............................................ 98 8-bit multiplexed mode ............................................ 101 a/d ........................................................................... 254 analog input model .................................................. 255 ausart receive .................................................... 244 ausart transmit ................................................... 242 baud rate generator .............................................. 203 capture mode operation ......................................... 166 comparator analog input model .............................. 265 comparator i/o operating modes ........................... 262 comparator output .................................................. 264 comparator voltage reference ............................... 268 comparator voltage reference output buffer example .................................... 269 compare mode operation ....................................... 167 connections for on-chip voltage regulator ........... 279 device clock .............................................................. 29 eusart receive .................................................... 228 eusart transmit ................................................... 226 external power-on reset circuit (slow v dd power-up) ........................................ 47 fail-safe clock monitor ........................................... 282 generic i/o port operation ...................................... 123 interrupt logic .......................................................... 108 mssp (i 2 c master mode) ........................................ 201 mssp (i 2 c mode) .................................................... 182 mssp (spi mode) ................................................... 173 on-chip reset circuit ................................................ 45 pic18f6xj11 ............................................................ 10 pic18f8xj11 ............................................................ 11 pll ............................................................................ 34 pic18f85j11 family ds39774c-page 382 preliminary ? 2007 microchip technology inc. portd and porte (parallel slave port) ............... 144 pwm operation (simplified) .................................... 169 reads from flash program memory ......................... 87 single comparator ................................................... 263 table read operation ................................................ 83 table write operation ................................................ 84 table writes to flash program memory .................... 89 timer0 in 16-bit mode .............................................. 148 timer0 in 8-bit mode ................................................ 148 timer1 (16-bit read/write mode) ............................ 152 timer1 (8-bit mode) ................................................. 152 timer2 ...................................................................... 158 timer3 (16-bit read/write mode) ............................ 160 timer3 (8-bit mode) ................................................. 160 watchdog timer ....................................................... 278 bn .................................................................................... 294 bnc .................................................................................. 295 bnn .................................................................................. 295 bnov ............................................................................... 296 bnz .................................................................................. 296 bor. see brown-out reset. bov .................................................................................. 299 bra .................................................................................. 297 brg. see baud rate generator. brgh bit txsta1 register ..................................................... 221 txsta2 register ..................................................... 240 brown-out reset (bor) ..................................................... 47 and on-chip voltage regulator ............................... 280 detecting .................................................................... 47 bsf .................................................................................. 297 btfsc ............................................................................. 298 btfss .............................................................................. 298 btg .................................................................................. 299 bz ..................................................................................... 300 c c compilers mplab c18 ............................................................. 336 mplab c30 ............................................................. 336 call ................................................................................ 300 callw ............................................................................. 329 capture (ccp module) ..................................................... 166 associated registers ............................................... 168 ccpr2h:ccpr2l registers ................................... 166 ccpx pin configuration ........................................... 166 software interrupt .................................................... 166 timer1/timer3 mode selection ................................ 166 capture/compare/pwm (ccp) ........................................ 163 capture mode. see capture. ccprxh register .................................................... 164 ccprxl register ..................................................... 164 ccpx mode and timer resources .......................... 164 compare mode. see compare. configuration ............................................................ 164 interaction of ccp1 and ccp2 for timer resources .............................................. 165 interconnect configurations ..................................... 164 clock sources .................................................................... 31 default system clock on reset ................................. 32 selection using osccon register ........................... 32 clrf ................................................................................ 301 clrwdt .......................................................................... 301 code examples 16 x 16 signed multiply routine .............................. 106 16 x 16 unsigned multiply routine .......................... 106 8 x 8 signed multiply routine .................................. 105 8 x 8 unsigned multiply routine .............................. 105 changing between capture prescalers ................... 166 computed goto using an offset value ................... 63 erasing a flash program memory row ..................... 88 fast register stack ................................................... 63 how to clear ram (bank 1) using indirect addressing ............................................ 76 implementing a real-time clock using a timer1 interrupt service ............................... 155 initializing porta .................................................... 124 initializing portb .................................................... 126 initializing portc ................................................... 128 initializing portd ................................................... 131 initializing porte .................................................... 134 initializing portf .................................................... 137 initializing portg ................................................... 139 initializing porth ................................................... 141 initializing portj .................................................... 142 loading the sspbuf (sspsr) register ................. 176 reading a flash program memory word .................. 87 saving status, wreg and bsr registers in ram ............................................. 122 writing to flash program memory ............................. 90 code protection ............................................................... 271 comf .............................................................................. 302 comparator ...................................................................... 261 analog input connection considerations ................ 265 associated registers ............................................... 265 configuration ........................................................... 262 effects of a reset .................................................... 264 interrupts ................................................................. 264 operation ................................................................. 263 operation during sleep ........................................... 264 outputs .................................................................... 263 reference ................................................................ 263 external signal ................................................ 263 internal signal .................................................. 263 response time ........................................................ 263 comparator specifications ............................................... 353 comparator voltage reference ....................................... 267 accuracy and error .................................................. 268 associated registers ............................................... 269 configuring .............................................................. 267 connection considerations ...................................... 268 effects of a reset .................................................... 268 operation during sleep ........................................... 268 compare (ccp module) .................................................. 167 associated registers ............................................... 168 ccpr2 register ...................................................... 167 ccpx pin configuration ........................................... 167 software interrupt .................................................... 167 special event trigger ...................................... 161, 167 timer1/timer3 mode selection ................................ 167 compare (ccp2 module) special event trigger .............................................. 258 computed goto ............................................................... 63 configuration bits ............................................................ 271 configuration bits, device ids associated registers ............................................... 272 ? 2007 microchip technology inc. preliminary ds39774c-page 383 pic18f85j11 family configuration register protection .................................... 284 core features easy migration ............................................................. 8 extended instruction set .............................................. 7 external memory bus ................................................... 7 memory options ........................................................... 7 nanowatt technology .................................................. 7 oscillator options and features .................................. 7 cpfseq .......................................................................... 302 cpfsgt .......................................................................... 303 cpfslt ........................................................................... 303 crystal oscillator/ceramic resonator ................................ 33 customer change notification service ............................ 391 customer notification service .......................................... 391 customer support ............................................................ 391 d data addressing modes ..................................................... 76 comparing addressing modes with the extended instruction set enabled ..................... 80 direct .......................................................................... 76 indexed literal offset ................................................. 79 bsr ................................................................... 81 instructions affected .......................................... 79 mapping access bank ....................................... 81 indirect ....................................................................... 76 inherent and literal .................................................... 76 data memory ..................................................................... 66 access bank .............................................................. 69 bank select register (bsr) ....................................... 66 extended instruction set ............................................ 79 general purpose registers ........................................ 69 memory maps pic18fx3j11/x4j11 devices ........................... 67 pic18fx5j11 devices ....................................... 68 special function registers ................................ 70 special function registers ........................................ 70 daw ................................................................................. 304 dc and ac characteristics graphs and tables .................................................. 373 dc characteristics pic18f85j11 family ............................................... 350 power-down and supply current ............................ 342 supply voltage ......................................................... 341 dcfsnz .......................................................................... 305 decf ............................................................................... 304 decfsz ........................................................................... 305 default system clock ......................................................... 32 details on individual family members ................................. 8 development support ...................................................... 335 device overview .................................................................. 7 features (64-pin devices) ........................................... 9 features (80-pin devices) ........................................... 9 direct addressing ............................................................... 77 e effect on standard pic18 instructions ............................. 332 effects of power-managed modes on various clock sources ............................................... 36 electrical characteristics .................................................. 339 enhanced universal synchronous asynchronous receiver transmitter (eusart). see eusart. envreg pin .................................................................... 279 equations a/d acquisition time ............................................... 256 a/d minimum charging time .................................. 256 calculating the minimum required acquisition time .............................................. 256 errata ................................................................................... 5 eusart asynchronous mode ................................................ 226 associated registers, receive ........................ 229 associated registers, transmit ....................... 227 auto-wake-up on sync break ......................... 230 break character sequence ............................. 231 receiver .......................................................... 228 setting up 9-bit mode with address detect ........................................ 228 transmitter ...................................................... 226 baud rate generator (brg) ................................... 221 associated registers ....................................... 221 auto-baud rate detect .................................... 224 baud rate error, calculating ........................... 221 baud rates, asynchronous modes ................. 222 high baud rate select (brgh bit) ................. 221 operation in power-managed modes .............. 221 sampling ......................................................... 221 control registers ..................................................... 217 synchronous master mode ...................................... 232 associated registers, receive ........................ 234 associated registers, transmit ....................... 233 reception ........................................................ 234 transmission ................................................... 232 synchronous slave mode ........................................ 235 associated registers, receive ........................ 236 associated registers, transmit ....................... 235 reception ........................................................ 236 transmission ................................................... 235 extended instruction set ................................................. 327 addfsr .................................................................. 328 addulnk ............................................................... 328 callw .................................................................... 329 considerations when enabling ................................ 332 movsf .................................................................... 329 movss .................................................................... 330 pushl ..................................................................... 330 subfsr .................................................................. 331 subulnk ................................................................ 331 syntax ...................................................................... 327 use with mplab ide tools ..................................... 334 extended microcontroller mode ......................................... 96 external memory bus ........................................................ 93 16-bit byte select mode ............................................ 99 16-bit byte write mode .............................................. 97 16-bit data width modes ........................................... 96 16-bit mode timing ................................................. 100 16-bit word write mode ............................................ 98 21-bit addressing ...................................................... 95 8-bit data width mode ............................................ 101 8-bit mode timing ................................................... 102 address and data line usage (table) ....................... 95 address and data width ............................................ 95 address shifting ........................................................ 95 and program memory modes .................................... 96 control ....................................................................... 94 i/o port functions ...................................................... 93 pic18f85j11 family ds39774c-page 384 preliminary ? 2007 microchip technology inc. operation in power-managed modes ...................... 103 wait states ................................................................. 96 weak pull-ups on port pins ....................................... 96 external oscillator modes ............ ...................................... 33 ec modes .................................................................. 34 hs modes .................................................................. 33 f fail-safe clock monitor ............................................ 271, 282 exiting fail-safe operation ...................................... 283 interrupts in power-managed modes ....................... 283 por or wake-up from sleep .................................. 283 wdt during oscillator failure ................................. 282 fast register stack ............................................................ 63 firmware instructions ....................................................... 285 flash configuration words ............................................... 271 mapping ................................................................... 271 flash program memory ...................................................... 83 associated registers ................................................. 91 control registers ....................................................... 84 eecon1 and eecon2 ..................................... 84 tablat (table latch) register ......................... 86 tblptr (table pointer) register ...................... 86 erase sequence ........................................................ 88 erasing ....................................................................... 88 operation during code-protect ................................. 91 reading ...................................................................... 87 table pointer boundaries based on operation ........................ 86 table pointer boundaries .......................................... 86 table reads and table writes .................................. 83 write sequence ......................................................... 89 writing ........................................................................ 89 unexpected termination .................................... 91 write verify ........................................................ 91 fscm. see fail-safe clock monitor. g goto ............................................................................... 306 h hardware multiplier .......................................................... 105 introduction .............................................................. 105 operation ................................................................. 105 performance comparison ........................................ 105 i i/o ports ........................................................................... 123 input voltage considerations ................................... 123 open-drain outputs ................................................. 124 output pin drive ....................................................... 123 pin capabilities ........................................................ 123 pull-up configuration ............................................... 124 i 2 c mode (mssp) ............................................................ 182 acknowledge sequence timing ............................... 210 associated registers ............................................... 216 baud rate generator ............................................... 203 bus collision during a repeated start condition .................. 214 during a stop condition ................................... 215 clock arbitration ....................................................... 204 clock stretching ....................................................... 196 10-bit slave receive mode (sen = 1) ............. 196 10-bit slave transmit mode ............................. 196 7-bit slave receive mode (sen = 1) ............... 196 7-bit slave transmit mode ............................... 196 clock synchronization and the ckp bit ................... 197 effects of a reset .................................................... 211 general call address support ................................. 200 i 2 c clock rate w/brg ............................................. 203 master mode ............................................................ 201 baud rate generator ...................................... 203 operation ......................................................... 202 reception ........................................................ 207 repeated start condition timing .................... 206 start condition timing ..................................... 205 transmission ................................................... 207 multi-master communication, bus collision and arbitration ................................................. 211 multi-master mode ................................................... 211 operation ................................................................. 187 read/write bit information (r/w bit) ............... 187, 189 registers ................................................................. 182 serial clock (sck/scl) ........................................... 189 slave mode .............................................................. 187 addressing ....................................................... 187 addressing masking ........................................ 188 reception ........................................................ 189 transmission ................................................... 189 sleep operation ....................................................... 211 stop condition timing ............................................. 210 incf ................................................................................ 306 incfsz ............................................................................ 307 in-circuit debugger .......................................................... 284 in-circuit serial programming (icsp) ...................... 271, 284 indexed literal offset addressing and standard pic18 instructions ............................. 332 indexed literal offset mode ............................................. 332 indirect addressing ............................................................ 77 infsnz ............................................................................ 307 initialization conditions for all registers ...................... 51?55 instruction cycle ................................................................ 64 clocking scheme ....................................................... 64 flow/pipelining ........................................................... 64 instruction set .................................................................. 285 addlw .................................................................... 291 addwf .................................................................... 291 addwf (indexed literal offset mode) .................... 333 addwfc ................................................................. 292 andlw .................................................................... 292 andwf .................................................................... 293 bc ............................................................................ 293 bcf ......................................................................... 294 bn ............................................................................ 294 bnc ......................................................................... 295 bnn ......................................................................... 295 bnov ...................................................................... 296 bnz ......................................................................... 296 bov ......................................................................... 299 bra ......................................................................... 297 bsf .......................................................................... 297 bsf (indexed literal offset mode) .......................... 333 btfsc ..................................................................... 298 btfss ..................................................................... 298 btg ......................................................................... 299 bz ............................................................................ 300 call ........................................................................ 300 clrf ....................................................................... 301 clrwdt ................................................................. 301 comf ...................................................................... 302 cpfseq .................................................................. 302 ? 2007 microchip technology inc. preliminary ds39774c-page 385 pic18f85j11 family cpfsgt .................................................................. 303 cpfslt ................................................................... 303 daw ......................................................................... 304 dcfsnz .................................................................. 305 decf ....................................................................... 304 decfsz ................................................................... 305 general format ........................................................ 287 goto ...................................................................... 306 incf ......................................................................... 306 incfsz .................................................................... 307 infsnz .................................................................... 307 iorlw ..................................................................... 308 iorwf ..................................................................... 308 lfsr ........................................................................ 309 movf ....................................................................... 309 movff .................................................................... 310 movlb .................................................................... 310 movlw ................................................................... 311 movwf ................................................................... 311 mullw .................................................................... 312 mulwf .................................................................... 312 negf ....................................................................... 313 nop ......................................................................... 313 opcode field descriptions ....................................... 286 pic18f85j11 family (table) .................................... 288 pop ......................................................................... 314 push ....................................................................... 314 rcall ..................................................................... 315 reset ..................................................................... 315 retfie .................................................................... 316 retlw .................................................................... 316 return .................................................................. 317 rlcf ........................................................................ 317 rlncf ..................................................................... 318 rrcf ....................................................................... 318 rrncf ................................ .................................... 319 setf ........................................................................ 319 setf (indexed literal offset mode) ........................ 333 sleep ..................................................................... 320 standard instructions ............................................... 285 subfwb .................................................................. 320 sublw .................................................................... 321 subwf .................................................................... 321 subwfb .................................................................. 322 swapf .................................................................... 322 tblrd ..................................................................... 323 tblwt ..................................................................... 324 tstfsz ................................................................... 325 xorlw .................................................................... 325 xorwf .................................................................... 326 intcon register rbif bit .................................................................... 126 intcon registers ........................................................... 109 inter-integrated circuit. see i 2 c mode. internal oscillator block ..................................................... 35 adjustment ................................................................. 35 intosc frequency drift ............................................ 35 intosc output frequency ........................................ 35 osc1, osc2 pin configuration ................................. 35 internal rc oscillator use with wdt .......................................................... 278 internal voltage regulator specifications ........................ 353 internet address ............................................................... 391 interrupt sources ............................................................. 271 a/d conversion complete ....................................... 255 capture complete (ccp) ........................................ 166 compare complete (ccp) ...................................... 167 interrupt-on-change (rb7:rb4) .............................. 126 tmr1 overflow ........................................................ 151 tmr2 to pr2 match (pwm) .................................... 169 tmr3 overflow ........................................................ 159 interrupts ......................................................................... 107 during, context saving ............................................ 122 intx pin ................................................................... 122 portb, interrupt-on-change .................................. 122 tmr0 ....................................................................... 122 interrupts, flag bits interrupt-on-change (rb7:rb4) flag (rbif bit) ................................................. 126 intosc, intrc. see internal oscillator block. iorlw ............................................................................. 308 iorwf ............................................................................. 308 ipr registers ................................................................... 118 l lfsr ............................................................................... 309 m master clear (mclr ) ......................................................... 47 master synchronous serial port (mssp). see mssp. memory organization ........................................................ 57 data memory ............................................................. 66 program memory ....................................................... 57 memory programming requirements .............................. 352 microchip internet web site ............................................. 391 microcontroller mode ......................................................... 96 migration between high-end device families ................. 379 oscillator differences .............................................. 380 peripherals .............................................................. 380 pin differences ........................................................ 380 power requirement differences .............................. 380 movf .............................................................................. 309 movff ............................................................................ 310 movlb ............................................................................ 310 movlw ........................................................................... 311 movsf ............................................................................ 329 movss ............................................................................ 330 movwf ........................................................................... 311 mplab asm30 assembler, linker, librarian .................. 336 mplab icd 2 in-circuit debugger .................................. 337 mplab ice 2000 high-performance universal in-circuit emulator ................................... 337 mplab integrated development environment software ............................................. 335 mplab pm3 device programmer ................................... 337 mplab real ice in-circuit emulator system ............... 337 mplink object linker/mplib object librarian ............... 336 mssp ack pulse ....................................................... 187, 189 control registers (general) ..................................... 173 module overview ..................................................... 173 spi master/slave connection .................................. 177 sspbuf register .................................................... 178 sspsr register ...................................................... 178 mullw ............................................................................ 312 mulwf ............................................................................ 312 pic18f85j11 family ds39774c-page 386 preliminary ? 2007 microchip technology inc. n negf ............................................................................... 313 nop ................................................................................. 313 o oscillator configuration ...................................................... 29 ec .............................................................................. 29 ecpll ........................................................................ 29 hs .............................................................................. 29 hspll ........................................................................ 29 internal oscillator block ............................................. 35 intosc ..................................................................... 29 intrc ........................................................................ 29 oscillator selection .......................................................... 271 oscillator start-up timer (ost) ......................................... 36 oscillator switching ............................................................ 31 oscillator transitions .......................................................... 32 oscillator, timer1 ..................................................... 151, 161 oscillator, timer3 ............................................................. 159 p packaging ........................................................................ 375 details ...................................................................... 376 marking .................................................................... 375 parallel slave port (psp) ................................................. 144 associated registers ............................................... 146 re0/rd pin .............................................................. 144 re1/wr pin ............................................................. 144 re2/cs pin .............................................................. 144 picstart plus development programmer .................... 338 pie registers ................................................................... 115 pin functions av dd .................................................................... 18, 27 av ss .................................................................... 18, 27 envreg .............................................................. 18, 27 mclr ................................................................... 12, 19 ra0/an0 .............................................................. 12, 19 ra1/an1 .............................................................. 12, 19 ra2/an2/v ref - .................................................... 12, 19 ra3/an3/v ref + ................................................... 12, 19 ra4/t0cki ........................................................... 12, 19 ra5/an4 .............................................................. 12, 19 ra6/osc2/clko ................................................ 12, 19 ra7/osc1/clki .................................................. 12, 19 rb0/int0 ............................................................. 13, 20 rb1/int1 ............................................................. 13, 20 rb2/int2 ............................................................. 13, 20 rb3/int3 ................................................................... 13 rb3/int3/ccp2 ......................................................... 20 rb4/kbi0 ............................................................. 13, 20 rb5/kbi1 ............................................................. 13, 20 rb6/kbi2/pgc .................................................... 13, 20 rb7/kbi3/pgd .................................................... 13, 20 rc0/t1oso/t13cki ........................................... 14, 21 rc1/t1osi/ccp2 ................................................ 14, 21 rc2/ccp1 ........................................................... 14, 21 rc3/sck/scl ..................................................... 14, 21 rc4/sdi/sda ...................................................... 14, 21 rc5/sdo ............................................................. 14, 21 rc6/tx1/ck1 ...................................................... 14, 21 rc7/rx1/dt1 ...................................................... 14, 21 rd0/ad0/psp0 .......................................................... 22 rd0/psp0 .................................................................. 15 rd1/ad1/psp1 .......................................................... 22 rd1/psp1 .................................................................. 15 rd2/ad2/psp2 ......................................................... 22 rd2/psp2 ................................................................. 15 rd3/ad3/psp3 ......................................................... 22 rd3/psp3 ................................................................. 15 rd4/ad4/psp4 ......................................................... 22 rd4/psp4 ................................................................. 15 rd5/ad5/psp5 ......................................................... 22 rd5/psp5 ................................................................. 15 rd6/ad6/psp6 ......................................................... 22 rd6/psp6 ................................................................. 15 rd7/ad7/psp7 ......................................................... 22 rd7/psp7 ................................................................. 15 re0/rd ..................................................................... 16 re0/rd /ad8 .............................................................. 23 re1/wr ..................................................................... 16 re1/wr /ad9 ............................................................. 23 re2/ad10/cs ............................................................ 23 re2/cs ...................................................................... 16 re3 ............................................................................ 16 re3/ad11 .................................................................. 23 re4 ............................................................................ 16 re4/ad12 .................................................................. 23 re5 ............................................................................ 16 re5/ad13 .................................................................. 23 re6 ............................................................................ 16 re6/ad14 .................................................................. 23 re7/ad15/ccp2 ....................................................... 23 re7/ccp2 ................................................................. 16 rf1/an6/c2out ................................................. 17, 24 rf2/an7/c1out ................................................. 17, 24 rf3/an8 .............................................................. 17, 24 rf4/an9 .............................................................. 17, 24 rf5/an10/cv ref ................................................ 17, 24 rf6/an11 ............................................................ 17, 24 rf7/an5/ss ........................................................ 17, 24 rg0 ..................................................................... 18, 25 rg1/tx2/ck2 ...................................................... 18, 25 rg2/rx2/dt2 ...................................................... 18, 25 rg3 ..................................................................... 18, 25 rg4 ..................................................................... 18, 25 rh0/a16 .................................................................... 26 rh1/a17 .................................................................... 26 rh2/a18 .................................................................... 26 rh3/a19 .................................................................... 26 rh4 ........................................................................... 26 rh5 ........................................................................... 26 rh6 ........................................................................... 26 rh7 ........................................................................... 26 rj0/ale .................................................................... 27 rj1/oe ...................................................................... 27 rj2/wrl ................................................................... 27 rj3/wrh ................................................................... 27 rj4/ba0 .................................................................... 27 rj5/ce ...................................................................... 27 rj6/lb ....................................................................... 27 rj7/ub ...................................................................... 27 v dd ...................................................................... 18, 27 v ddcore /v cap ..................................................... 18, 27 v ss ...................................................................... 18, 27 pinout i/o descriptions pic18f6xj11 ............................................................ 12 pic18f8xj11 ............................................................ 19 pir registers ................................................................... 112 ? 2007 microchip technology inc. preliminary ds39774c-page 387 pic18f85j11 family pll ..................................................................................... 34 ecpll oscillator mode .............................................. 34 hspll oscillator mode .............................................. 34 pop ................................................................................. 314 por. see power-on reset. porta associated registers ............................................... 125 lata register .......................................................... 124 porta register ...................................................... 124 trisa register ........................................................ 124 portb associated registers ............................................... 127 latb register .......................................................... 126 portb register ...................................................... 126 rb7:rb4 interrupt-on-change flag (rbif bit) ................................................. 126 trisb register ........................................................ 126 portc associated registers ............................................... 130 latc register ......................................................... 128 portc register ...................................................... 128 rc3/sck/scl pin ................................................... 189 trisc register ........................................................ 128 portd ............................................................................ 144 associated registers ............................................... 133 latd register ......................................................... 131 portd register ...................................................... 131 trisd register ........................................................ 131 porte associated registers ............................................... 136 late register .......................................................... 134 porte register ...................................................... 134 re0/rd pin .............................................................. 144 re1/wr pin ............................................................. 144 re2/cs pin .............................................................. 144 trise register ........................................................ 134 portf associated registers ............................................... 138 latf register .......................................................... 137 portf register ...................................................... 137 trisf register ........................................................ 137 portg associated registers ............................................... 140 latg register ......................................................... 139 portg register ...................................................... 139 trisg register ........................................................ 139 porth associated registers ............................................... 141 lath register ......................................................... 141 porth register ...................................................... 141 trish register ........................................................ 141 portj associated registers ............................................... 143 latj register .......................................................... 142 portj register ....................................................... 142 trisj register ......................................................... 142 power-managed modes ..................................................... 37 and spi operation ................................................... 181 clock sources ............................................................ 37 clock transitions and status indicators ..................... 38 entering ...................................................................... 37 exiting idle and sleep modes .................................... 43 by interrupt ........................................................ 43 by reset ............................................................ 43 by wdt time-out .............................................. 43 without an oscillator start-up delay .................. 43 idle modes ................................................................. 41 pri_idle .......................................................... 42 rc_idle ........................................................... 43 sec_idle ......................................................... 42 multiple sleep commands ......................................... 38 run modes ................................................................ 38 pri_run ........................................................... 38 rc_run ............................................................ 40 sec_run ......................................................... 38 selecting .................................................................... 37 sleep mode ............................................................... 41 summary (table) ........................................................ 37 power-on reset (por) ...................................................... 47 power-up delays ............................................................... 36 power-up timer (pwrt) ............................................. 36, 48 time-out sequence ................................................... 48 prescaler, capture ........................................................... 166 prescaler, timer0 ............................................................ 149 prescaler, timer2 ............................................................ 170 pri_idle mode ................................................................. 42 pri_run mode ................................................................. 38 program counter ............................................................... 61 pcl, pch and pcu registers .................................. 61 pclath and pclatu registers .............................. 61 program memory extended instruction set ........................................... 78 flash configuration words ........................................ 58 hard memory vectors ................................................ 58 instructions ................................................................ 65 two-word .......................................................... 65 interrupt vector .......................................................... 58 look-up tables .......................................................... 63 memory maps ............................................................ 57 hard vectors and configuration words .................................. 58 modes ........................................................................ 59 extended microcontroller ................................... 59 extended microcontroller (address shifting) ...................................... 60 memory access (table) ...................................... 60 microcontroller ................................................... 59 reset vector .............................................................. 58 program memory modes operation of the external memory bus ..................... 96 program verification and code protection ...................... 284 programming, device instructions ................................... 285 psp. see parallel slave port. pspmode bit (pspcon register) ................................. 144 pulse-width modulation. see pwm (ccp module). push ............................................................................... 314 push and pop instructions .............................................. 62 pushl ............................................................................. 330 pwm (ccp module) associated registers ............................................... 171 duty cycle ............................................................... 170 example frequencies/resolutions .......................... 170 period ...................................................................... 169 setup for pwm operation ....................................... 171 tmr2 to pr2 match ................................................ 169 q q clock ............................................................................ 170 pic18f85j11 family ds39774c-page 388 preliminary ? 2007 microchip technology inc. r ram. see data memory. rc_idle mode .................................................................. 43 rc_run mode .................................................................. 40 rcall .............................................................................. 315 rcon register bit status during initialization .................................... 50 reader response ............................................................ 392 register file ....................................................................... 69 register file summary ................................................. 71?74 registers adcon0 (a/d control 0) ......................................... 251 adcon1 (a/d control 1) ......................................... 252 adcon2 (a/d control 2) ......................................... 253 baudcon1 (baud rate control 1) ......................... 220 ccpxcon (ccpx control) ...................................... 163 cmcon (comparator control) ................................ 261 config1h (configuration 1 high) .......................... 273 config1l (configuration 1 low) ............................ 273 config2h (configuration 2 high) .......................... 275 config2l (configuration 2 low) ............................ 274 config3h (configuration 3 high) .......................... 276 config3l (configuration 3 low) ...................... 59, 276 cvrcon (comparator voltage reference control) ........................................... 267 devid1 (device id register 1) ................................ 277 devid2 (device id register 2) ................................ 277 eecon1 (eeprom control 1) .................................. 85 intcon (interrupt control) ...................................... 109 intcon2 (interrupt control 2) ................................. 110 intcon3 (interrupt control 3) ................................. 111 ipr1 (peripheral interrupt priority 1) ........................ 118 ipr2 (peripheral interrupt priority 2) ........................ 119 ipr3 (peripheral interrupt priority 3) ........................ 120 memcon (external memory bus control) ................ 94 osccon (oscillator control) .................................... 30 osctune (oscillator tuning) ................................... 31 pie1 (peripheral interrupt enable 1) ........................ 115 pie2 (peripheral interrupt enable 2) ........................ 116 pie3 (peripheral interrupt enable 3) ........................ 117 pir1 (peripheral interrupt request (flag) 1) ............................................. 112 pir2 (peripheral interrupt request (flag) 2) ............................................. 113 pir3 (peripheral interrupt request (flag) 3) ............................................. 114 pspcon (parallel slave port control) .................... 145 rcon (reset control) ....................................... 46, 121 rcsta1 (eusart receive status and control) .......................................... 219 rcsta2 (ausart receive status and control) .......................................... 239 sspcon1 (mssp control 1, i 2 c mode) ................. 184 sspcon1 (mssp control 1, spi mode) ................. 175 sspcon2 (mssp control 2, i 2 c master mode) ............................................. 185 sspcon2 (mssp control 2, i 2 c slave mode) ....... 186 sspstat (mssp status, i 2 c mode) ....................... 183 sspstat (mssp status, spi mode) ...................... 174 status ..................................................................... 75 stkptr (stack pointer) ............................................ 62 t0con (timer0 control) .......................................... 147 t1con (timer1 control) .......................................... 151 t2con (timer2 control) .......................................... 157 t3con (timer3 control) .......................................... 159 txsta1 (eusart transmit status and control) ..................................................... 218 txsta2 (ausart transmit status and control) ..................................................... 238 wdtcon (watchdog timer control) ...................... 278 reset ............................................................................. 315 reset ................................................................................. 45 brown-out reset (bor) ............................................. 45 mclr reset, during power-managed modes .......... 45 mclr reset, normal operation ................................ 45 power-on reset (por) .............................................. 45 reset instruction ..................................................... 45 stack full reset ......................................................... 45 stack underflow reset .............................................. 45 watchdog timer (wdt) reset .................................. 45 resets .............................................................................. 271 brown-out reset (bor) ........................................... 271 oscillator start-up timer (ost) ............................... 271 power-on reset (por) ............................................ 271 power-up timer (pwrt) ......................................... 271 retfie ............................................................................ 316 retlw ............................................................................ 316 return .......................................................................... 317 return address stack ........................................................ 61 return stack pointer (stkptr) ........................................ 62 rlcf ............................................................................... 317 rlncf ............................................................................. 318 rrcf ............................................................................... 318 rrncf ........................ .................................................... 319 s sck ................................................................................. 173 sdi ................................................................................... 173 sdo ................................................................................. 173 sec_idle mode ............................................................... 42 sec_run mode ................................................................ 38 serial clock, sck ............................................................ 173 serial data in (sdi) .......................................................... 173 serial data out (sdo) ..................................................... 173 serial peripheral interface. see spi mode. setf ................................................................................ 319 slave select (ss ) ............................................................. 173 sleep ............................................................................. 320 sleep osc1 and osc2 pin states ...................................... 36 software simulator (mplab sim) ................................... 336 special event trigger. see compare (ccp module). special features of the cpu ........................................... 271 spi mode (mssp) associated registers ............................................... 181 bus mode compatibility ........................................... 181 effects of a reset .................................................... 181 enabling spi i/o ...................................................... 177 master mode ............................................................ 178 master/slave connection ......................................... 177 operation ................................................................. 176 operation in power-managed modes ...................... 181 serial clock .............................................................. 173 serial data in ........................................................... 173 serial data out ........................................................ 173 slave mode .............................................................. 179 slave select ............................................................. 173 slave select synchronization .................................. 179 spi clock ................................................................. 178 typical connection .................................................. 177 ? 2007 microchip technology inc. preliminary ds39774c-page 389 pic18f85j11 family ss .................................................................................... 173 sspov ............................................................................. 207 sspov status flag ......................................................... 207 sspstat register r/w bit ............................................................. 187, 189 stack full/underflow resets .............................................. 63 status register .............................................................. 75 subfsr .......................................................................... 331 subfwb .......................................................................... 320 sublw ............................................................................ 321 subulnk ........................................................................ 331 subwf ............................................................................ 321 subwfb .......................................................................... 322 swapf ............................................................................ 322 t table pointer operations (table) ........................................ 86 table reads/table writes ................................................. 63 tblrd ............................................................................. 323 tblwt ............................................................................. 324 timer0 .............................................................................. 147 associated registers ............................................... 149 clock source select (t0cs bit) ............................... 148 interrupt .................................................................... 149 operation ................................................................. 148 prescaler .................................................................. 149 switching assignment ...................................... 149 prescaler assignment (psa bit) .............................. 149 prescaler select (t0ps2:t0ps0 bits) ..................... 149 prescaler. see prescaler, timer0. reads and writes in 16-bit mode ............................ 148 source edge select (t0se bit) ................................ 148 timer1 .............................................................................. 151 16-bit read/write mode ........................................... 153 associated registers ............................................... 155 interrupt .................................................................... 154 operation ................................................................. 152 oscillator .......................................................... 151, 153 layout considerations ..................................... 154 oscillator, as secondary clock .................................. 31 overflow interrupt .................................................... 151 resetting, using the ccpx special event trigger ...................................... 154 tmr1h register ...................................................... 151 tmr1l register ....................................................... 151 use as a clock source ............................................ 153 use as a real-time clock ....................................... 154 timer2 .............................................................................. 157 associated registers ............................................... 158 interrupt .................................................................... 158 operation ................................................................. 157 output ...................................................................... 158 pr2 register ............................................................ 169 tmr2 to pr2 match interrupt .................................. 169 timer3 .............................................................................. 159 16-bit read/write mode ........................................... 161 associated registers ............................................... 161 interrupt .................................................................... 161 operation ................................................................. 160 oscillator .......................................................... 159, 161 overflow interrupt .................................................... 159 special event trigger (ccp) .................................... 161 tmr3h register ...................................................... 159 tmr3l register ....................................................... 159 timing diagrams a/d conversion ....................................................... 372 acknowledge sequence .......................................... 210 asynchronous reception ................................. 229, 245 asynchronous transmission ........................... 227, 243 asynchronous transmission (back-to-back) ......................................... 227, 243 automatic baud rate calculation ............................ 225 auto-wake-up bit (wue) during normal operation ............................................ 230 auto-wake-up bit (wue) during sleep ................... 230 baud rate generator with clock arbitration ............ 204 brg overflow sequence ........................................ 225 brg reset due to sda arbitration during start condition ................................................. 213 bus collision during a repeated start condition (case 1) ........................................... 214 bus collision during a repeated start condition (case 2) ........................................... 214 bus collision during a start condition (scl = 0) ......................................... 213 bus collision during a stop condition (case 1) ........................................... 215 bus collision during a stop condition (case 2) ........................................... 215 bus collision during start condition (sda only) ...................................... 212 bus collision for transmit an d acknowledge .......... 211 capture/compare/pwm (ccp1, ccp2) .................. 361 clko and i/o .......................................................... 358 clock synchronization ............................................. 197 clock/instruction cycle .............................................. 64 eusart/ausart synchronous receive (master/slave) ................................................. 370 eusart/ausart synchronous transmission (master/slave) ................................................. 370 example spi master mode (cke = 0) ..................... 362 example spi master mode (cke = 1) ..................... 363 example spi slave mode (cke = 0) ....................... 364 example spi slave mode (cke = 1) ....................... 365 external clock (all modes except pll) ................... 356 external memory bus for sleep (extended microcontroller mode) .............................. 100, 102 external memory bus for tblrd (extended microcontroller mode) .............................. 100, 102 fail-safe clock monitor ........................................... 283 first start bit timing ................................................ 205 i 2 c bus data ............................................................ 367 i 2 c bus start/stop bits ............................................ 366 i 2 c master mode (7 or 10-bit transmission) ........... 208 i 2 c master mode (7-bit reception) ......................... 209 i 2 c slave mode (10-bit recepti on, sen = 0) .......... 193 i 2 c slave mode (10-bit reception, sen = 0, admsk = 01001) ............................................ 194 i 2 c slave mode (10-bit recepti on, sen = 1) .......... 199 i 2 c slave mode (10-bit transmission) .................... 195 i 2 c slave mode (7-bit reception, sen = 0) ............ 190 i 2 c slave mode (7-bit reception, sen = 0, admsk = 01011) ............................................ 191 i 2 c slave mode (7-bit reception, sen = 1) ............ 198 i 2 c slave mode (7-bit transmission) ...................... 192 i 2 c slave mode general call address sequence (7 or 10-bit address mode) ............................. 200 pic18f85j11 family ds39774c-page 390 preliminary ? 2007 microchip technology inc. i 2 c stop condition receive or transmit mode ................................................. 210 mssp i 2 c bus data ................................................. 368 mssp i 2 c bus start/stop bits ................................. 368 parallel slave port (psp) read ............................... 146 parallel slave port (psp) write ............................... 145 pwm output ............................................................ 169 repeated start condition ......................................... 206 reset, watchdog timer (wdt), oscillator start-up timer (ost) and power-up timer (pwrt) ..... 359 send break character sequence ............................ 231 slave synchronization ............................................. 179 slow rise time (mclr tied to v dd , v dd rise > t pwrt ) ............................................ 49 spi mode (master mode) ......................................... 178 spi mode (slave mode, cke = 0) ........................... 180 spi mode (slave mode, cke = 1) ........................... 180 synchronous reception (master mode, sren) .............................. 234, 248 synchronous transmission .............................. 232, 246 synchronous transmission (through txen) ....................................... 233, 247 time-out sequence on power-up (mclr not tied to v dd ), case 1 ....................... 49 time-out sequence on power-up (mclr not tied to v dd ), case 2 ....................... 49 time-out sequence on power-up (mclr tied to v dd , v dd rise < t pwrt ) ........... 48 timer0 and timer1 external clock .......................... 360 transition for entry to idle mode ................................ 42 transition for entry to sec_run mode .................... 39 transition for entry to sleep mode ............................ 41 transition for two-speed start-up (intrc to hspll) ........................................... 281 transition for wake from idle to run mode .............. 42 transition for wake from sleep (hspll) ................. 41 transition from rc_run mode to pri_run mode ................................................. 40 transition from sec_run mode to pri_run mode (hspll) .................................. 39 transition to rc_run mode ..................................... 40 timing diagrams and specifications capture/compare/pwm requirements (ccp1, ccp2) ................................................. 361 clko and i/o requirements ................................... 358 eusart/ausart synchronous receive requirements ................................................... 370 eusart/ausart synchronous transmission requirements ................................................... 370 example spi mode requirements (master mode, cke = 0) .................................. 362 example spi mode requirements (master mode, cke = 1) .................................. 363 example spi mode requirements (slave mode, cke = 0) .................................... 364 example spi slave mode requirements (cke = 1) ................................. 365 external clock requirements .................................. 356 i 2 c bus data requirements (slave mode) .............. 367 i 2 c bus start/stop bits requirements (slave mode) ................................................... 366 internal rc accuracy ............................................... 357 mssp i 2 c bus data requirements ......................... 369 mssp i 2 c bus start/stop bits requirements .......... 368 pll clock ................................................................ 357 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements ........................................ 359 timer0 and timer1 external clock requirements ........................................ 360 top-of-stack access .......................................................... 61 tstfsz ........................................................................... 325 two-speed start-up ................................................. 271, 281 two-word instructions example cases .......................................................... 65 v v ddcore /v cap pin .......................................................... 279 voltage reference specifications .................................... 353 voltage regulator (on-chip) ........................................... 279 brown-out reset (bor) ........................................... 280 low-voltage detection (lvd) .................................. 279 operation in sleep mode ......................................... 280 power-up requirements .......................................... 280 w watchdog timer (wdt) ........................................... 271, 278 associated registers ............................................... 278 control register ....................................................... 278 programming considerations .................................. 278 wcol ...................................................... 205, 206, 207, 210 wcol status flag ................................... 205, 206, 207, 210 www address ................................................................ 391 www, on-line support ................... ................................... 5 x xorlw ............................................................................ 325 xorwf ........................................................................... 326 ? 2007 microchip technology inc. preliminary ds39774c-page 391 pic18f85j11 family the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following informa- tion: ? product support ? data sheets and errata, appli- cation notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of micro- chip sales offices, distributors and factory repre- sentatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notifi- cation and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representa- tive or field application engineer (fae) for support. local sales offices are also available to help custom- ers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com pic18f85j11 family ds39774c-page 392 preliminary ? 2007 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39774c pic18f85j11 family 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? ? 2007 microchip technology inc. preliminary ds39774c-page 393 pic18f85j11 family product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device pic18f63j11/64j11/65j11 (1) , pic18f83j11/84j11/85j11 (1) , pic18f63j11/64j11/65j11t (2) , pic18f83j11/84j11/85j11t (2) temperature range i = -40 c to +85 c (industrial) package pt = tqfp (thin quad flatpack) pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic18f85j11-i/pt 301 = industrial temp., tqfp package, qtp pattern #301. b) pic18f63j11t-i/pt = tape and reel, industrial temp., tqfp package. note 1: f = standard voltage range 2: t = in tape and reel ds39774c-page 394 preliminary ? 2007 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway habour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7250 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - gumi tel: 82-54-473-4301 fax: 82-54-473-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - penang tel: 60-4-646-8870 fax: 60-4-646-5086 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 12/08/06 |
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